JPH0316219A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce electrode wiring resistance as well as prevent breakage by a method wherein polycrystalline silicon is embedded on a first electrode wiring layer to be flattened on a contact window. CONSTITUTION:After an interlayer insulation film 13 is formed on a semiconductor substrate 11 and a contact window 14 is opened on a specific position by etching, a first aluminum electrode wiring layer 15 is adhered on a diffusion layer region 12 of the semiconductor substrate exposed at the contact window by deposition or the like. After polycrystal silicon 18 is adhered by low pressure CVD on the layer 15, resist 19 is applied and polycrystal silicon except on a recess of the first aluminum electrode wiring layer 15 is removed by etch back to leave the polycrystalline silicon 18 only on the recess to be embedded and flattened. A second electrode wiring layer 20 is adhered on this. Thus flattening of the electrode layer of the contact window 14 can be done as well as electrode wiring resistance can be decreased thereby preventing breakage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which the electrode wiring layer is planarized at the contact portion between the electrode wiring layer and a diffusion layer in a semiconductor substrate. .

Conventionally, as shown in FIG. 2, BI'SG is formed as an interlayer insulation II 23 on the whole surface of a semiconductor substrate 21 (b), and after a contact window 24 is opened (e), a BI'SG is formed on the whole surface of a semiconductor substrate 21. The first aluminum wiring layer 25 is formed by vapor deposition or the like (d).

Problems to be Solved by the Invention Conventionally, however, as shown in Fig. 2, the aluminum wiring layer used as the electrode wiring was formed by vapor deposition.
A contact window with a step has a thick part 27 at the center of the bottom and a thin part 26 at the peripheral corners of the bottom. As a result, the resistance of the electrode wiring increases, and sometimes the wiring breaks at the corners of the periphery. Further, there is a problem in that the level difference in the semiconductor device increases near the contact window.

In view of these points, the present invention aims to provide a method for manufacturing a semiconductor device that can planarize the electrode wiring layer of the contact window and reduce the electrode wiring resistance.

Means for Solving the Problems In order to achieve the above object, the present invention includes a step of depositing a glabella insulating film on a semiconductor substrate, a step of opening a contact window in the interlayer insulating film, and a step of forming a contact window portion in the interlayer insulating film. A step of depositing a first electrode wiring layer on the diffusion layer of the semiconductor substrate exposed to the semiconductor substrate, and depositing polycrystalline silicon or m a step of embedding a compound of group V and group V or a compound of group II and group VI; and a step of embedding a second
This is a method of manufacturing a semiconductor device, characterized by a step of depositing an electrode wiring layer.

Function: By this method of manufacturing a semiconductor device, the electrode wiring layer of the contact window can be planarized and the electrode wiring resistance can be reduced.

Further, a break in the first electrode wiring at the bottom of the contact window is relieved by the buried polycrystalline silicon or compound and the second electrode wiring layer above.

EXAMPLES Below, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to FIG.

FIG. 1 is a sectional view showing a contact portion of an embodiment of the semiconductor device of the present invention.

After forming BPSG as an interlayer insulating film 13 on the semiconductor substrate 11 (b) and opening a contact window 14 at a predetermined location by etching (C), the diffusion layer of the semiconductor substrate exposed in the contact window portion is removed. A first aluminum electrode wiring M15 is deposited on the region l2 by vapor deposition or the like (d), and polycrystalline silicon 18 is deposited on the upper part of the first aluminum electrode wiring layer 15.
After depositing by low pressure CVD (e), a resist 19 is applied (f), and polycrystalline silicon other than the concave portions of the first aluminum electrode wiring layer 15 is removed by etchback, and polycrystalline silicon 18 is deposited only in the concave portions. After filling and planarizing (g), a second electrode wiring layer 20 is deposited on the first aluminum electrode wiring layer 15 and the polycrystalline silicon 18 buried in the contact recess.

As described above, according to this embodiment, even if the first aluminum wiring layer 15 is disconnected at the bottom of the contact window, it is relieved by the polycrystalline silicon in the recess and the second aluminum wiring layer 20 above. In the embodiment, conductive polycrystalline silicon is buried in the contact window recess, but compounds of Groups II and V of the Periodic Table of Elements or compounds of Groups II and VI may also be buried.

Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, by burying polycrystalline silicon on the first electrode wiring layer in the contact window for planarization, electrode wiring resistance can be reduced and disconnection can be prevented. It can be eliminated. As a result, the reliability of the electrode wiring layer can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a contact portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a contact portion of a conventional semiconductor device. l1... Semiconductor substrate, 12... Diffusion layer region, 13... Interlayer insulating film, l4...
Contact window, 15...First aluminum wiring layer, 1
6... Part where the aluminum wiring is thinner at the corner around the contact, 17... Part where the aluminum wiring is thicker at the center of the contact, 18... Polycrystalline silicon. , 19... Resist, 20...
・Second aluminum wiring layer, 21... Semiconductor substrate, 2
2... Diffusion layer region, 23... Interlayer insulating film, 24... Contact window, 25...
Aluminum wiring layer, 26... Part where the aluminum wiring is thinner at the corner around the contact, 27...
The part where the aluminum wiring becomes thick at the center of the contact.

Claims (3)

[Claims] (1) A step of depositing an interlayer insulating film on a semiconductor substrate, a step of opening a contact window in the interlayer insulating film, and a step of depositing a first contact window on the diffusion layer region of the semiconductor substrate exposed in the contact window portion. A method for manufacturing a semiconductor device, comprising the steps of depositing an electrode wiring layer, and burying polycrystalline silicon in the recessed portion of the first electrode wiring layer at the contact window portion by low pressure CVD and etchback. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (2) depositing a second electrode wiring layer over the first electrode wiring layer and the contact window in which polycrystalline silicon is embedded. (3) Manufacturing the semiconductor device according to claim 1, characterized in that, instead of polycrystalline silicon, compounds of groups III and V or compounds of groups II and VI in the periodic table of elements are embedded in the contact window. Method.