JPH0316648B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-on reset circuit used in various electronic devices.

Power-on reset circuits that have been commonly used include those shown in FIGS. 1 through 3.

The circuit shown in Figure 1, when the power is turned on, the MOS
Transistor 1 turns on and charging current flows through capacitor C. Charging of capacitor C progresses,
The output of inverter 2 remains “H” until the potential at point A exceeds the threshold level of inverter 2.
(high), a reset signal is output, and when point A exceeds the threshold level, the output of inverter 2 becomes "L" (low) and the reset signal is turned off. The circuit in Figure 2 is similar to the circuit in Figure 1.
A resistor R is connected in place of the MOS transistor 1, and the operation is substantially the same as the circuit shown in FIG.

In the circuit shown in Figure 3, when the power is turned on, +V rises, and when it exceeds the threshold level of MOS transistor 3, the MOS transistor turns on.
Furthermore, the potential at point B divided by resistors R1 and R2 is
When the threshold level of the MOS transistor 4 is exceeded, the MOS transistor 4 is turned on and the input of the inverter 5 becomes "L". Therefore, the output of the inverter 6, which was output as a reset signal, also drops from "H" to "L".

The drawbacks of the conventional power-on reset circuits described above are that the circuits shown in FIGS. 1 and 2 do not operate with a power supply that rises slowly, and the circuit shown in FIG. 3 works even with a power supply that rises slowly. Even when the device is stationary, current flows and consumes power.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power-on reset circuit which eliminates the drawbacks of the conventional circuits described above, operates even with a slow-starting power supply, and consumes low power when at rest.

In order to achieve the above object, the power-on reset circuit of the present invention is composed of a pair of C-MOS inverters 11 and 12, and one C-MOS inverter 11 is connected in series between a power supply and ground.
A first type MOS transistor 13, a second N type MOS transistor 13
MOS transistor 14, and a third N-type MOS transistor 15.
The gates of the MOS transistors 13, 14, and 15 are commonly connected, and the connection point between the first and second MOS transistors 13, 14 is used as an output section.
The other C-MOS inverter 12 is connected in series between the power supply and the ground, a P-type fourth MOS transistor 16, a P-type fifth MOS transistor 17,
Consisting of an N-type sixth MOS transistor 18,
Fourth, fifth, and sixth MOS transistors 16, 1
7 and 18 gates are commonly connected, and the 5th and 6th gates are connected in common.
An unbalanced flip-flop 10 in which the connection point of MOS transistors 17 and 18 is used as an output part, and the gate connection part of both C-MOS inverters 11 and 12 and the output part are cross-connected.
, reset signal output circuits 19 and 20 which receive the output of the unbalanced flip-flop 10 and derive a reset signal, and which are connected between the output section of the unbalanced flip-flop 10 and ground, and which output an external signal. It is composed of a MOS transistor 21 which is turned on when receiving the reset signal and releases the reset signal.

Hereinafter, the present invention will be explained in more detail with reference to Examples.

FIG. 4 is a connection diagram of a power-on reset circuit showing one embodiment of the present invention. In the same figure, 10
is an unbalanced flip-flop, and is composed of a pair of inverters 11 and 12.

Inverter 11 is P-type MOS transistor 13
and N-type MOS transistors 14 and 15 are connected in series between the +V power supply and the ground GND, and each MOS
The gates of transistors 13, 14, and 15 are commonly connected. In addition, the inverter 12 is of P type.
MOS transistors 16, 17 and N-type MOS transistor 18 are connected in series between +V power supply and ground GND, and each MOS transistor 16, 17,
Eighteen gates are commonly connected. Both have a C-MOS configuration.

However, the inverter 11 is grounded to the output terminal P1.
A series circuit of transistors 14 and 15 is connected between GND,
A transistor 13 is connected between the output terminal P1 and the +V power supply,
In contrast, the inverter 12 is connected to the output terminal P.
A transistor 18 is connected between the output terminal P2 and the ground GND, and a series circuit of transistors 16 and 17 is connected between the output terminal P2 and the +V power supply.
The two on-resistances are different and are unbalanced.

Inverters 19 and 20 are connected to the output terminal P1 of the inverter 11, and the reset signal RS is output from the output terminal of the inverter 20.

Further, an N-type MOS transistor 21 is connected between the output terminal P1 of the inverter 11 and GND, and this transistor 21 is turned on by a clock signal CP input from the outside.

A dummy inverter 22 having the same shape as the inverter 19 and a dummy N-type MOS transistor 23 having the same shape as the transistor 21 are connected to the output terminal P2 of the inverter 12, and the output sides of the inverters 11 and 12 are configured to be symmetrical. There is.

Next, the operation of the embodiment circuit configured as described above will be explained.

When the power is turned on and the power supply voltage rises as shown in FIG. This "H" signal passes through inverters 19 and 20, and a reset signal RS (see FIG. 5b) is derived to reset a functional circuit section not shown.

When the clock signal CP [see Fig. 5c] is inputted from the outside, the transistor 21 is turned on by the clock signal CP, and the output terminal P1 of the inverter 11 is forced to "L". The level also drops to "L" and the reset is released.

When the output terminal P1 of the inverter 11 falls to "L", the output terminal P2 of the inverter 12 corresponds to this.
becomes “H”. This state is maintained even if the clock signal CP is no longer input and the transistor 21 is turned off.

In this embodiment circuit, after the power is turned on and the reset signal RS becomes "H", if the clock signal CP is not input, the reset signal RS is maintained at "H".

According to this invention, a pair of C-MOS inverters are used, and one of the inverters is of P type, and the first
MOS transistor, N-type second and third MOS
The other inverter is a P-type fourth and fifth MOS transistor, and an N-type sixth MOS transistor.
Since it is composed of MOS transistors and forms an unbalanced flip-flop, it can operate even with a slow-starting power supply, and when it is stationary, almost no current flows, resulting in low power consumption. Therefore,
The power-on reset circuit of the present invention is suitable for application to ICs for battery-operated electronic devices.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams showing conventional power-on reset circuits, FIG. 4 is a connection diagram of a power-on reset circuit showing an embodiment of the present invention, and FIG. 5 is a circuit diagram showing a conventional power-on reset circuit.
The figure is a waveform diagram for explaining the operation of the power-on reset circuit. 10: Unbalanced flip-flop, 11,
12, 19, 20, 22: Inverter, 21, 2
3: MOS transistor.

Claims (1)

[Claims] 1. A P-type first circuit consisting of a pair of C-MOS inverters 11 and 12, with one C-MOS inverter 11 connected in series between a power supply and ground.
It consists of a MOS transistor 13, a second N-type MOS transistor 14, and a third N-type MOS transistor 15, and the gates of the first, second, and third MOS transistors 13, 14, and 15 are commonly connected. First and second MOS transistors 13, 14
The connection point of C-
a P-type fourth MOS transistor 16 with which the MOS inverter 12 is connected in series between the power supply and ground;
Consisting of a P-type fifth MOS transistor 17 and an N-type sixth MOS transistor 18, the fourth, fifth, and sixth MOS transistors 16, 17, and 18
The gates of the C-MOS inverters 11 and 1 are connected in common, and the connection point between the fifth and sixth MOS transistors 17 and 18 is used as an output section, and both C-MOS inverters 11 and 1
an unbalanced flip-flop 10 in which the gate connection part and the output part of the two unbalanced flip-flops are cross-connected; reset signal output circuits 19 and 20 that receive the output of the unbalanced flip-flop 10 and derive a reset signal; A power-on reset circuit comprising a MOS transistor 21 connected between the output part of the unbalanced flip-flop 10 and ground, turned on when receiving an external signal, and canceling the reset signal.