JPS6281123A - Cmos inverter circuit - Google Patents

Abstract

PURPOSE:To prevent latchup by a through-current and to reduce a dynamic current consumption by providing a timing control circuit giving the 1st and 2nd signals deviated for a prescribed time based on an input signal respectively to each gate electrode of a PMOS and an NMOS. CONSTITUTION:A delay circuit 61 outputs an output signal retarding an input signal V1 slightly and gives the signal to an OR gate 62 and an AND gate 63. The OR circuit 62 ORs the input signal V1 and the output signal of the delay circuit 61 and the result is given to a gate of a PMOS 3. The AND gate 63 ANDs the input signal V1 and the output signal of the delay circuit 61 and gives the result to a gate electrode of an NMOS 4. Since the PMOS 3 and the NMOS 4 are turned off simultaneously at a period T, the latchup due to a through-current is prevented and the dynamic current consumption is reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides an 0MO5 (complementary type M
The present invention relates to a CMOS inverter circuit having an OS (transistor) configuration.

(Conventional technology) Conventionally, as a technology in this field, IEICE technical report, 5S
There was one described in D82-39 (1982) P, l-7. The configuration will be explained below using figures.

FIG. 2 is a general circuit diagram of a conventional CMOS inverter circuit. This CMOS inverter circuit has an input terminal l
and an output terminal 2, and a P-channel MOS transistor (hereinafter referred to as PMOS) is connected between the input and output terminals 1 and 2.
3 and N-channel MOS transistor (hereinafter referred to as NHO
2) 4 are connected in cascade.

That is, the PMOS 3 has its source electrode connected to the power supply VDD, its drain electrode connected to the drain electrode and output terminal 2 of the NMOS 4, and its gate electrode connected to the input terminal. Further, the NMOS 4 has its source electrode connected to the power supply vss (=o), and its gate electrode connected to the input terminal 1, respectively.

This type of (:MOS inverter circuit), when a pulsed input signal VI is applied, outputs PMOS3 or NMOS4.
is turned on, the input signal v■ is inverted, and the output signal vO of the potential VDD or vSS is output from the output terminal 2.

FIG. 3 is a schematic cross-sectional view of the structure of the CMOS inverter circuit in FIG. 1. A P-type isolation layer (hereinafter referred to as P-well) 11 is formed within the N-type substrate 10 . A pair of P' regions 12 and 13 are formed on the N-type substrate 10, and a PMOS 3 is constituted by a source electrode 14, a drain electrode 15, and a gate electrode 1B formed thereon.

A pair of N'' regions 17 and 18 are formed in the P well 1, and an NMOS 4 is formed by a source electrode 19, a drain electrode 20, and a gate electrode 21 formed thereon.

In this CMOS inverter circuit, N type substrate lO and P
Parasitic transistors 31, 32, 33.3 in the well 11
4 is formed.

FIG. 4 is an equivalent circuit of the CMOS inverter circuit of FIG. 3, taking into account parasitic transistors and resistance. P
Parasitic transistors 31 to 34 and an N-type substrate 10 are connected between the drain electrodes of MOS3 and NMOS4 and the output terminal 2.
resistances 41 to 45, and distributed resistance 46 in the P well 11
~50 are connected.

In such an equivalent circuit, latch-up may occur for reasons explained below.

Latch-up is a phenomenon specific to CMO3 circuits.
When an integrated circuit (hereinafter referred to as IC) is in operation, a PMPM structure risk phenomenon occurs inside the IC due to input noise, excessive current flows between the power supplies VDD and VS2, and even if the disturbance signal is cut off, the abnormal current continues. A phenomenon that causes damage or destruction.

In the equivalent circuit of FIG. 4, when a voltage higher than the potential vDD is applied to the output terminal 2 or its current is injected, a current flows through the path of the output terminal 2 → transistor 31 → resistor 45 → resistor 41 → power supply VDII. . Therefore, the transistor 31 is turned on, and its collector current flows from the output terminal 2 to the transistor 31 to the resistor 49 to the resistor 50 to the power supply VSS.

Since the collector current causes a potential drop across the resistor 50, the base potential of the transistor 320 increases, turning the transistor 32 on. When transistor 32 is turned on, its collector current causes a potential drop across resistor 41, turning transistor 33 on. Then,
Since the collector currents of transistors 32 and 33 supply each other's base currents, even if the overvoltage or injection current at output terminal 2 disappears, the power supply VD[) -VS
Current continues to flow between the two.

In such a rough stub state, the current between the power supplies VI)D and VS2 cannot be cut off unless the power is turned off.

Therefore, the above-mentioned document discloses a technique for a substrate structure to prevent such latch-up.

(Problems to be solved by the invention) However, in the conventional CMOS input/hater circuit,
Not only is it time-consuming to manufacture the substrate structure, but there is also the problem that latch-up cannot be completely prevented for the following reasons.

Now, consider a case where an input signal VI as shown in the signal waveform diagram of FIG. 5 is input to the input terminal 1 of FIG. 2. Usually, C
:Inside the MOS circuit, in order to reduce the chip size of the IC, the threshold value of PMOS3 is designed to be high and the threshold value of NMOS4 is designed to be low. Therefore, the OS on PMO93 and N
The on/off state of 4 is as shown in Figure 5, and the PMOS
A period t occurs during which NMOS 3 and NMOS 4 are simultaneously on. At this time, since a through current occurs inside the IC, the power supply potential VDD fluctuates as shown in FIG. Then, C
The output signal vO of the MOS inverter circuit has a potential V[l[
There were times when the value was higher than +, and there was a risk that a rat-up as described in (1) above would occur. Furthermore, even if latch-up does not occur, there is a problem in that dynamic current consumption increases.

The present invention provides a CMOS inverter circuit that solves the problems of the prior art, such as latch-up due to through current and increase in dynamic current consumption.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides PMOS and N
A CMOS inverter circuit in which MOS is connected in series and outputs an output signal obtained by inverting the input signal applied to the gate electrodes of the PMOS and NMOS, and outputs first and second signals shifted by a predetermined time based on the input signal. and sends the first and second signals to the PMOS and N
A timing control circuit is provided to apply signals to each gate electrode of the MOS.

(Function) According to the present invention, since the CMOS inverter circuit is configured as described above, the timing control circuit works to shift the timing of turning on the PMOS and the timing of turning on the NMOS according to its output signal. . This can prevent the generation of through current.

Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a CMOS inverter circuit showing an embodiment of the present invention. Note that the same elements as the conventional elements in FIG. 2 are given the same reference numerals.

This CMOS inverter circuit differs from conventional circuits in that a timing control circuit 60 is provided between input terminal 1 and PMOS 3 and NMOS 4, and the output signal of this circuit 60 turns PMOS 3 and NMOS 4 on and off. That's true.

Here, the timing control circuit 60 includes a delay circuit 61 composed of an integrating circuit, etc., a logical sum gate (hereinafter referred to as an OR gate) 62 of two human power outputs, and an AND gate (hereinafter referred to as an AND gate) of two human power outputs. 63 (referred to as a gate).

The delay circuit 81 has its input terminal connected to the input terminal 1, and its input terminal connected to one input terminal of the OR gate 62 and the AND gate 63, respectively. The other input terminal of the OR gate 62 is connected to the input terminal l, and its output terminal is connected to the PMOS
3, respectively. Also, A
The other input terminal of the ND gate 63 is connected to the input terminal 1,
The output ends thereof are connected to the gate electrodes of the NMOS 4, respectively.

FIG. 6 shows an example of the structure of the delay circuit 61, which is formed of a T-shaped integrating circuit using a capacitor C.

Next, the operation of the CMOS inverter circuit configured as described above will be explained with reference to the signal waveform diagram of FIG.

Assume now that an input signal vI consisting of a trapezoidal pulse wave is applied to the delay circuit B1 and the OR gate 62 via the input terminal 1. The delay circuit 61 outputs an output signal that is slightly delayed from the input signal Vl, and outputs an output signal that is slightly delayed from the input signal Vl.
give to The OR circuit 62 connects the input signal VI and the delay circuit 61
The logical OR with the output signal of is applied to the gate of PMOS3. At this time, the output signal of the OR gate 62 (first
signal) is at H level, PMOS3 is off and L
It is in the on state when it is at level. Further, the AND gate 63 performs a logical product of the input signal v■ and the output signal of the delay circuit 61, and applies it to the gate electrode of the NMOS4. At this time, the output signal (second signal) of the AND gate 63 becomes H.
When the level is low, the NMOS 4 is on, and when the level is low, the NMOS 4 is off.

Then, during period T in FIG. 7, PMOS3 and NM
Since the OS 4 is turned off at the same time, launch-up due to through current can be prevented and dynamic current consumption can be reduced. Note that the time period T may be appropriately selected depending on the operating speed of the circuit and the like.

Therefore, in this embodiment, after PMOS3 changes from on state to completely off state, NMOS4 turns on state, and 8
Since the PMOS 3 is turned on after the MO94 is completely turned off, it is possible to easily and accurately prevent latch amplifiers and reduce dynamic current consumption.

Therefore, in Bi-CMOS where roughness is likely to occur, 0MO close to bipolar (analog part)
It is effective to provide a timing control circuit 60 in the circuit 3.

Note that in the above embodiments, the timing control circuit 60 can also be configured using other logic circuits.

(Effects of the Invention) As explained in detail above, according to the present invention, the PMOS
Since the timing of turning on the NMOS and the timing of turning on the NMOS are staggered, it can be expected that latch-up due to through current can be prevented and dynamic current consumption can be reduced.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a CMOS inverter circuit of the present invention, Fig. 2 is a circuit diagram of a conventional CMOS inverter circuit, Fig. 3 is a schematic cross-sectional view of the structure of Fig. 2, and Fig. 4 is an equivalent circuit of Fig. 3. 5 is a signal waveform diagram of the circuit of FIG. 2, FIG. 6 is a circuit diagram of the delay circuit in FIG. 1, and FIG. 7 is a signal waveform diagram of the circuit of FIG. 3...PMOS, 4...NMOS, 8
0...timing control circuit, 61...
Delay circuit, 62...OR gate, S3...
...AND gate. Applicant's representative: Sei 3 Kakiki: PA
71O5 4: NMOS 6MO51'' of the present invention, /JX'-ta 4th figure 1, 2nd figure ------m-------------VSS signal waveform diagram of 2nd figure Figure 5 Signal waveform of delay circuit No. 17 in Figure 1 Figure 7

Claims (1)

[Scope of Claims] A CMOS inverter circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series and outputs an output signal that is an inversion of an input signal applied to the gate electrodes of both transistors, comprising: 1st and 2nd shifted by a predetermined time
A CMOS inverter circuit comprising a timing control circuit that outputs a signal and applies the first and second signals to respective gate electrodes of both of the transistors.