JPH03167986A - High efficiency coding device - Google Patents

Abstract

PURPOSE:To improve the compression rate and to prevent the deterioration in the resolution by combining the time space subsampling and the frame omission processing and using an original data so as to decide the interpolation method decreasing the error most at the sender side. CONSTITUTION:A rate conversion circuit 4 brings a luminance signal Y to 3/4 data rate to reduce the transmission data quantity and a color difference signal into 1/2 data rate and the data are converted into line sequential data. A subsampling and block processing circuit 5 applies the time space subsampling processing and block processing and a frame omission and ADRC encoder 6 is provided after the subsampling and block processing circuit 5. A three dimension ADRC coding using the frame omission processing in common is coded. Interpolation outputs I1-I4 are fed respectively to subtraction circuits 24, 25, 26 and 27. The data of a noticed picture element (y) is fed to the subtraction circuits 24-27 and the error between the true value of the noticed picture element (y) and the interpolated output is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device that compresses the amount of transmitted information of a digital image signal by subsampling and adaptive frame dropping.

[Summary of the Invention] The present invention provides a high resolution system in which a plurality of pixel data contained in a three-dimensional block spanning n frames of a digital television signal is thinned out by subsampling, and the remaining pixel data after the thinning process is transmitted. In the efficiency encoding device, multiple types of interpolation methods using temporally and spatially adjacent transmitted pixel data are prepared for each non-transmitted pixel data to be thinned out in each block, and for each interpolation method, the true value and the interpolated An arithmetic circuit that calculates the absolute value of the difference in values, a circuit that generates a flag signal representing the optimal interpolation method for each block based on the output of the arithmetic circuit, and a circuit that calculates the absolute value of the difference in values. a switching circuit that switches between a first mode for transmitting pixel data and a second mode for transmitting pixel data for m frames of n frames in block units; A circuit that detects the difference between an interpolated value obtained by interpolating non-transmitted pixel data of (n-m) frames of the block of interest from transmitted pixel data of It has a control signal generation circuit that generates a control signal for the switching circuit, and a transmission circuit that transmits the flag signal, pixel data to be transmitted from the switching circuit, and the control signal. Since the present invention is a hybrid high-efficiency encoding method using three-dimensional subsampling and adaptive frame dropping, the compression ratio can be extremely high, and the quality of the restored image can be improved.

[Conventional technology]

Since a digital image signal has a larger amount of data than a digital audio signal, it is required to reduce the amount of data to be transmitted in a digital VTR or the like whose transmission capacity is limited. Many techniques have been proposed for this compression method.

A known method for compressing image information by removing spatial redundancy is to reduce the sampling frequency by subsampling. For example, a method is known in which data is thinned out to two by subsampling and a flag is transmitted to indicate the direction in which the thinned out data is to be interpolated. In other words, on the transmitting side, there are two methods: one is to interpolate using the data located above and below the thinned out pixel, and the other is to interpolate using the data located to the left and right of the thinned out pixel.
The interpolation method with the smaller error is detected, and a 1-bit flag indicating this interpolation method is set. This flag is transmitted instead of the pixel data of the interpolation point. In the above-mentioned subsampling, data compression was insufficient because a flag indicating the interpolation method was transmitted corresponding to all interpolation points. In order to solve the problem that the compression ratio is restricted due to the flag signal, the applicant of the present application proposed a method using a two-dimensional set of multiple pixels as described in Japanese Patent Application No. 1982-26228. We propose a high-efficiency encoding method that forms a representative flag for each block and transmits the representative flag. For each of multiple pixels in a block, an interpolation method with the smallest error among multiple types of interpolation methods is detected, majority logic is applied to the detected interpolation method, and the block corresponds to the majority interpolation method. Each flag signal is emitted.

Furthermore, a high-efficiency encoding device has been proposed that can remove redundancy in the level direction of each pixel data and reduce the number of quantization bits of each pixel data. As one of the methods, the applicant calculates the dynamic range, which is the difference between the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application Laid-Open No. 144989/1989.
We have proposed an adaptive encoding device that performs encoding adapted to this dynamic range. Also, JP-A-62-9262
As described in Japanese Patent No. 0, an adaptive encoding device has been proposed that performs encoding adapted to the dynamic range of a three-dimensional block formed from pixels of regions included in each of a plurality of frames. Furthermore, JP-A-62-12
As described in Japanese Patent No. 8621, a variable length encoding method has been proposed in which the number of bits changes depending on the dynamic range so that the maximum distortion that occurs during quantization is constant.

Furthermore, in order to compress the amount of transmitted data by removing redundancy in the time direction, the movement of images within a block is detected, and in the case of a still image block, the average value of the pixels of a three-dimensional block is detected. Adaptive frame dropping and AD for transmitting information
A hybrid system combining RC has been proposed by the applicant of the present application (see the specification of Japanese Patent Application No. 60-247840).

By combining the above-mentioned subsampling that transmits a flag signal indicating the optimal interpolation method on a block-by-block basis, adaptive frame dropping, and ADRC as necessary,
It becomes possible to significantly compress the amount of transmitted data.

[Problem to be solved by the invention]

However, subsampling in which a representative flag is set for each two-dimensional block has the disadvantage that the resolution is degraded, particularly in a stationary part.

In addition, adaptive frame dropping is performed based on determining whether the block is a moving image.
It is often determined that the block is a still image block (referred to as a still block). In a static block, the average value of spatially corresponding pixel data of two regions is expressed. This average value is transmitted instead of the original pixel data. On the receiving side, the average value is repeatedly used as restored pixel data for two frame periods. In this case, one of two spatially adjacent blocks within the same frame may be determined to be a stationary block, and the other may be determined to be a moving block. If these blocks are in an area where they should have the same luminance level, block distortion occurs where the level difference between adjacent blocks becomes noticeable.

Therefore, an object of the present invention is to provide a high-efficiency encoding device that can significantly increase the compression rate, prevent resolution deterioration in stationary parts, and prevent block distortion from occurring during frame drop processing. It is about providing.

[Means to solve the problem]

The present invention provides a high-efficiency encoding device in which a plurality of pixel data contained in a three-dimensional block spanning n frames of a digital television signal is thinned out by subsampling, and the remaining pixel data after the thinning process is transmitted. For each non-transmitted pixel data to be thinned out in each block, multiple types of interpolation methods using temporally and spatially adjacent transmitted data are prepared, and for each interpolation method, the absolute value of the difference between the true value and the interpolated value is calculated. Calculating means (24, 25, 26, 27, 28) for calculating values; and means (34) for generating a flag signal Fy representing the optimal interpolation method for each block based on the output of the calculating means (24-28). , 35, 36, 37, 39), a first mode that transmits all pixel data for n frames of each subsampled block, and a second mode that transmits pixel data for m frames of n frames. a switching means (48) for switching the mode in block units; and an interpolated value obtained by interpolating non-transmission pixel data of (n-m) frames of the attention block from at least m frames of transmission pixel data of the attention block in the second mode. and control signal generating means (53) for generating a control signal SJ for the switching means (51) regarding the block of interest based on the output of the detecting means (5l). , 54), and a transmission means (7) for transmitting the flag signal Fy, transmission pixel data from the switching means, and control signal SJ. [Operation] A three-dimensional block is constructed by two areas An and An+1 belonging to two temporally consecutive frames. Half of the pixel data of this block is thinned out by subsampling. The pixel data to be thinned out is an interpolation point that is corrected on the receiving side.

A plurality of types of interpolation are performed using a plurality of transmitted pixel data temporally and spatially adjacent to an interpolation point. Interpolated data Il, ■2, ■3, obtained by each of these interpolations,
■4 is compared with the true value of the pixel data at the interpolation point, and the error data between the interpolation data and the true value is determined. The error data is aggregated for each block and the aggregate value is calculated. A flag signal F) F indicating the interpolation method that minimizes this total value is output. This flag signal F)f is generated for each block. On the receiving side, an interpolation method is selected with reference to the flag signal Fy, and therefore, an interpolation method with the minimum error is selected. Since the minimum aggregate error value is detected, it is possible to prevent an interpolation method from being set that would result in an extremely large interpolation error for one or a small number of pixels. Therefore, it is possible to prevent noticeable noise from occurring in the restored image. Image data subjected to spatiotemporal subsampling is subjected to frame dropping and ADRC encoding processing.

When data of non-transmitted pixels whose frames have been dropped is linearly corrected on the receiving side, the subtraction circuit 51 calculates the difference between the interpolated value obtained by linear interpolation and the true value of the non-transmitted pixels. 1 of this difference
When the cumulative value of blocks is large, no pieces are dropped,
When this is small, pieces are dropped. Therefore, in the restored image, block distortion is prevented from occurring between blocks where frame drop is performed and blocks where frame drop is not performed.

The above-mentioned flag signal Fy, the encoded output of ADRC, and the control signal (frame drop flag) SJ are supplied to the frame forming circuit 7 and converted into the form of transmission data. [Examples] Examples of the present invention will be described below with reference to the drawings. This explanation is given in the following order. a. Overall structure of one embodiment b. Subsampling and blockingC. Piece dropping and ADRC d. Variation a. Overall Structure of an Embodiment FIG. 1 shows the structure when the present invention is applied to compression of a color video signal. Component signals of a luminance signal Y, a (RY) signal, and a (BY) signal are supplied to an input terminal indicated by 1. This component signal is converted into an 8-bit digital signal by the A/D converter 2. The sampling frequencies of the luminance signal Y and the two color difference signals are 13.5MHz and 6.75k, respectively, and the so-called (4:2:2) component signals are A/D.
Obtained from converter 2. The output signal of the A/D converter 2 is supplied to a valid area extraction circuit 3, and only valid image data is extracted. Valid image data is supplied to rate conversion circuit 4. In the rate conversion circuit 4, in order to reduce the amount of data to be transmitted, the luminance signal Y has a data rate of 3/4, and the color difference signal has a data rate of 1/4.
/2 data rate and is converted to line sequential data. Therefore, from the rate conversion circuit 4 (3:1
:0) component signal is obtained. After the above-mentioned preprocessing is performed, the data is compressed to a target data rate by high-efficiency encoding.

The output signal of the rate conversion circuit 4 is supplied to a subsampling and blocking circuit 5. This circuit 5 performs spatiotemporal subsampling processing and blocking processing. After the subsampling and blocking circuit 5, a frame dropping and ADRC encoder 6 is provided. Here, three-dimensional ADRC encoding is performed in combination with frame drop processing.

The flag signal generated by subsampling, the AD of transmitted pixel data. An RC encoded output, a control signal indicating the presence or absence of frame dropping, etc. are supplied to the framing circuit 7. Further, in the framing circuit 7, an error correction code is encoded.
The transmission data taken out to the output terminal 8 of the framing circuit 7 is recorded on a magnetic tape by a rotary head via, for example, a channel encoding encoder, a recording amplifier, etc. Since the rate of this transmitted data is sufficiently low, it is possible to record data using a tape head mechanism similar to that of a consumer analog VTR. Note that the luminance signal Y and color difference signals (RY) and (B-Y) are separately encoded with high efficiency. However, since the high-efficiency encoding process is the same in both cases, the high-efficiency encoding of the luminance signal will be described below.

b. Subsampling and blocking In this embodiment, a television screen is divided into a large number of regions, three-dimensional blocks are constructed from two regions belonging to two consecutive frames, and an interpolation method is determined for each three-dimensional block. At the same time, encoding is performed to compress the amount of data. As the image of one frame is shown in Fig. 3,
(MXN), area All A12,...
, AMN takes shape. The next frame in time is divided in the same way, and the areas All', A12'..., AMN
' is expressed. Then, two areas All and A11', A12 and A12', . . ., A
Three-dimensional blocks are shaped by MN and AMN', respectively. One area is, for example, (4 lines x 8 pixels), and therefore, the number of pixels in one block is 64.

Fig. 4 shows temporal changes in blocks at the same spatial position. In Fig. 4, An is an area of size (4 lines x 8 pixels) of the n-th frame Fn. Yes, An+1 is the (n+1)th frame F n+1
The area is (4 lines x 8 pixels). These two areas An and An,+1 are at corresponding positions between the two frames; An is, for example, A12 in FIG. 3, and A n +1 is A12'.
In FIG. 4, the solid lines indicate the lines of the first field, and the dashed lines indicate the lines of the second field.
The above-mentioned areas An and A n + 1 constitute the ■block. Furthermore, FIG. 4 shows a subsampling pattern, in which pixels indicated by x are thinned out by subsampling. In the example shown in FIG. 4, the subsampling phase is inverted every line and every two frames. Therefore,
The sampling grid patterns of the two regions within the block are the same.

FIG. 2 shows the structure of the subsampling and blocking circuit 5 in this embodiment, and 11 is an input terminal for the digital video signal from the rate conversion circuit 4. In FIG. The input data is a data sequence in scan order rather than block order. This manual data is used for delay circuits 12, 13 and 1.
4 in cascade connection and the delay circuit 15. Delay circuits 16, 17, and 18 are connected to the connection points of delay circuits 13 and 14. These delay circuits are provided to simultaneously extract a plurality of pieces of data that are spatially and temporally close to the pixel of interest to be interpolated. Delay circuits 13, 14, and 15 indicated by SD have a delay time equal to the sampling period of input data, and delay circuit 16 has a delay time corresponding to l horizontal time (IH).
7 has a delay time corresponding to l frame time (FL).

n+1th frame Fn+1 of the above three-dimensional block
A plurality of pixels around the non-transmission pixel y included in the area An+1 are given symbols as shown in FIG. Pixel d is transmission pixel data included in another block area two lines below area Ana1. The data of these pixels is transferred to the non-transmission pixel y, which is focused on the output side of the delay circuit 13.
As shown in FIG. 2, at the timing when
, are generated on the output side of l5, respectively. On the output side of the delay circuit 17, the (n-1)th frame Fn-, which is two frames before, is output.
Pixel data (not shown in FIG. 4, but this pixel data is represented by e) at a position corresponding to the pixel of interest y in area An-1 of No. 1 is generated. On the output side of the delay circuit l, pixel data f at a position corresponding to the target pixel y in the area An of the frame Fn one frame before is generated. This pixel data f should be thinned out by subsampling. Using the data of the pixels surrounding the pixel of interest y, multiple types, for example, four types of interpolation similar to those provided on the receiving side are performed simultaneously, and interpolation outputs 11 to I4 are produced. The interpolation output I1 is an intra-field horizontal interpolation output and is generated by the adder circuit 19.

1 1='A(a+b).

Interpolation output (2) is an intra-frame vertical interpolation output, which is input to the adder circuit 20 and processed.

I2='4(c+d).

The interpolation output I3 is a four-point average interpolation within the frame, and is added by the addition circuit 21.

1 3 = '/i ( a + b + c + d
). The adder circuits 19, 20, and 2l have the function of adding the addition result to A.

Interpolation output (4) is inter-frame interpolation, and interpolation is performed using pixel data e from two frames before or pixel data f from one frame before.

I4=e or f The output data of the delay circuit 17 and the output data of the delay circuit 18 are provided to the switching circuit 22. one of which is selected by the switching circuit 22 as the interpolation output I4.
The switching circuit 22 is switched for each frame by the control signal from the terminal 23, and subsampling is performed in the pattern shown in FIG. There is data f, and in the area of the subsequent frame, there is transmission pixel data e two frames before. The switching circuit 22 selects these transmitted pixel data. When focusing on the above-mentioned non-transmitted pixel data y, the switching circuit 22 selects the transmitted pixel data e two frames before. The above-mentioned interpolation output I1-14 is the subtraction circuit 24, 25, 26
and 27, respectively. These subtraction circuits 24-2
7 is supplied with the data of the pixel of interest y, and the pixel of interest, y
The error between the true value of and the interpolated output is calculated. Subtraction circuit 24
27 output signals are combined into one channel of data and supplied to the absolute value conversion circuit 28. (8 bits x 4-32 bits) error data from the absolute value converting circuit 28 is supplied to one input terminal a of the sampling switch 29. The other input terminal b of the sampling switch 29 has
Data of the pixel of interest is supplied from the delay circuit l3.

Sampling switch 29 is controlled by a sampling pulse from terminal 30. This sampling pulse has a phase that inverts the phase of subsampling every line and every two frames. Therefore, at the output terminal C of the sampling switch 29, the true value of 8-bit pixel data is located at the sampling point to be transmitted (indicated by a circle in FIG. 4), and the sampling point to be thinned out (indicated by a circle in FIG. At the interpolation point (indicated by x), 32-bit error data converted to an absolute value is located.

The output signal of the sampling switch 29, in which pixel data and error data are time-division multiplexed, is supplied to the blocking circuit 3l and converted into the three-dimensional block order as described above. The output signal of the blocking circuit 31 is supplied to the distribution circuit 32. The distribution circuit 32 outputs the pixel data. The data series Ds and the data series Es of error data are separated and extracted. The pixel data series Ds is frame dropped and A
The signal is supplied to the DRC encoder 6 and undergoes encoding processing as described below.

The error data series Es from the distribution circuit 32 is transmitted to the distribution circuit 3.
3. The distribution circuit 33 divides the 32-bit parallel error data into four 8-bit error data. 4
error data are supplied to aggregation circuits 34, 35, 36 and 37, respectively. A block cycle reset pulse is supplied from a terminal 38 to these counting circuits 34 to 37. By the counting circuits 34 to 37, 32 in 1 block
Error data regarding interpolation points are aggregated. In this case, a structure can be used in which the error data is converted to an n-th power sum and the n-th power sum is totaled. The output signals of the aggregation circuits 34 to 37 are detected by the minimum value detection circuit 39
is supplied to The minimum value detection circuit 39 detects the minimum value among the aggregated values of error data, and outputs an interpolation selection flag Far. In other words, find the interpolation method that minimizes the error. A 2-bit interpolation selection flag Fy is generated. As an example, when selecting intra-field horizontal interpolation, an interpolation selection flag Fy of (00) is generated, and when selecting intra-frame vertical interpolation, an interpolation selection flag Fy of (01) is generated, and four points within a frame are generated. When average value interpolation is selected, interpolation selection flag Fy (10) is generated, and when interframe interpolation is selected, interpolation selection flag F7 (11) is generated. This interpolation selection flag Fy is supplied to the framing circuit 7.

What kind of interpolation selection flag Fy is generated depends on the image content of the block. For example, if the block image is a still image, (11) is generated as the interpolation selection flag Fy, and interframe interpolation is performed on the receiving side. This inter-frame interpolation prevents resolution deterioration in stationary parts. Although not shown, on the receiving side, data processing is performed in the reverse order of that on the transmitting side. The received data is processed by the frame decomposition circuit.
In addition to error correction, the encoded output of ADRC, frame drop flag SJ, and interpolation selection flag F y. The encoded output and frame drop flag SJ are supplied to the ADRC decoder, the pixel data of the transmitted sample points are restored, and the restored data is supplied to the interpolation circuit. The interpolation circuit is designed to selectively perform four types of interpolation for each block with respect to non-transmission pixels thinned out by subsampling, and the type of interpolation is selected by an interpolation selection flag Far. Restored data with the original number of pixels is obtained from the interpolation circuit. C. Frame Drop and ADRC FIG. 5 shows the configuration of an example of the frame drop and ADRC encoder 6, and the distribution circuit 32 converted into block order.
An output signal (data after subsampling processing) is supplied to the input terminal 41. This input data is transmitted to the 4 frame delay circuit 42, the A block delay circuit 43, the multiplication circuit 44,
The signal is supplied to a gate circuit 45 and a three-dimensional ADRC encoder 46. The output signal of the gate circuit 45 is two-dimensional ADRC
ADRC encoder 46 supplied to encoder 47
and 47 are respectively supplied to input terminals A and B of a switching circuit 48, and one of the encoded outputs is selected for its output terminal C. The encoded output is an additive code (
DR, MIN) and a code signal DT corresponding to each pixel.

The encoded output from the output terminal C of the switching circuit 48 is supplied to the framing circuit 7. The frame forming circuit 7 is also supplied with a 1-bit frame dropping flag SJ corresponding to the presence or absence of frame dropping. In this embodiment, in the second mode in which frame dropping is performed, the code signal DT of the temporally later area Aij'(An+1) of the two areas constituting one block is transmitted, and the code signal DT of the previous area Aij'(An+1) is transmitted. Code signal DT in area Aij(An) is not transmitted. The two-dimensional ADRC encoder 47 encodes 16 pixel data compressed into A by frame dropping. The three-dimensional ADRC encoder 46 is
32 pixel data are encoded in the lth mode in which no frames are dropped. On the receiving side, for blocks in which frames have been dropped, data in the frame-dropped area is interpolated by linear interpolation (primary interpolation) using transmitted pixel data. It is determined whether or not to drop frames based on the magnitude of the difference between the interpolated value obtained by the same interpolation method used on the receiving side and the true value. The multiplication circuit 44 triples the value of the input signal of the 4-frame delay circuit 42, and the multiplication output is supplied to the addition circuit 49. The adder circuit 49 is supplied with the output signal of the 4-frame delay circuit 42. The output signal of the adder circuit 49 is supplied to the bit shift circuit 50, and is set to a value of 2. An interpolated value is obtained at the output of the bit shift circuit 50. The output signal of the bit shift circuit 50 is subtracted from the output signal of the % block delay circuit 43 by a subtraction circuit 51. The output signal of the subtraction circuit 51 is converted into an absolute value by an absolute value conversion circuit 52. This absolute value is the difference between the true value and the interpolated value for each pixel of interest, and the accumulation circuit 53 calculates the cumulative value of the difference for one block. This accumulated value is supplied to a comparison circuit 54 and compared with a reference value from a terminal 55. Accumulation circuit 53
Instead, a maximum value detection circuit that detects the maximum value among the differences of one block may be used. The comparison circuit 54 detects the magnitude relationship between the cumulative value and the reference value, and when the cumulative value is smaller than the reference value, an output signal of "1" is generated, which means that frame dropping processing is possible. Conversely, when the cumulative value is greater than the reference value, an output signal of "0'" is generated, which means that frame drop processing cannot be performed. The output signal of the comparison circuit 54 is held in the latch 56,
The output signal of the latch 56 is supplied to the switching circuit 48 and the framing circuit 7 as a frame dropping flag SJ, respectively.

In the second mode in which frame drop processing is performed, that is, when the frame drop flag SJ is "1", input terminal A and output terminal C of the switching circuit 48 are selected, and the encoded output of the ADRC encoder 47 is selected. Ru. On the other hand, in the first mode in which frame dropping processing is not performed, that is, the frame dropping flag S is
When J is “0”, input terminal B of the switching circuit 48
and output terminal C are selected, and the encoded output of ADRC encoder 46 is selected. The gate circuit 45 allows the pixel data of the area A n +1, which is temporally subsequent to the two areas An and An+1 constituting one block, to pass through in response to the control signal P2 from the control signal generation circuit 57. The control signal generation circuit 57 has a terminal 58
A clock signal P1 having a block period is supplied from the input terminal 1, and a control signal P2 synchronized with input data is generated. Further, the control signal P2 is used as an enable signal for the accumulation circuit 53, and the accumulation operation is enabled during the period when the control signal P2 is "1". Further, the control signal P2 is supplied to the differentiating circuit 59, and the differential pulse P3 from the differentiating circuit 59 is supplied to the accumulating circuit 53 as its reset signal.

An example of the three-dimensional ADRC encoder 46 is shown in FIG.
Input data from an input terminal 61 is supplied to a maximum value and minimum value detection circuit 62 and a delay circuit 63. The detection/output circuit 62 detects the maximum value +[MAX and the minimum value MIN among the 32 pixel data of one block. Delay circuit 6
3 is the time to detect the maximum value MAX and the minimum value MIN;
It delays data. The subtraction circuit 64 calculates (MAX-MAIN), and the dynamic range DR is obtained from the subtraction circuit 64. The dynamic range DR is supplied to the ROM 66, and when obtaining a 4-bit code signal, for example, the dynamic range DR is set to 1/16. The quantization step Δ is obtained from this ROM 66.

In the subtraction circuit 65, the minimum value MIN is subtracted from the pixel data from the delay circuit 63, and pixel data PDI from which the minimum value has been removed is obtained from the subtraction circuit 65.

The data PDI normalized by minimum value removal and the quantization step Δ from the subtraction circuit 65 are supplied to the quantization circuit 67 . Original number of bits from quantization circuit 67 (8 bits)
A 4-bit code signal DT having a smaller number of bits is obtained. The quantization circuit 67 has a dynamic range DR.
Performs quantization adapted to. For the sake of simplicity, in the example of 2-bit quantization, as shown in Figure 7A, the minimum value is removed at the quantization step Δ, which divides the dynamic range DR into equal parts (2" = 4). PDI is divided, and the value obtained by rounding down the quotient to an integer is used as the code signal DT.
! The child conversion circuit 67 may be a division circuit or a ROM. In FIG. 7, LO, LL, L2, and L3 indicate decoding levels.

As the quantization method in the quantization circuit 67, as shown in FIG. 7B, a method may be used in which a value matching the maximum value MAX and the minimum value MIN is obtained as the decoding level. The two-dimensional ADRC encoder 47 is the three-dimensional ADR encoder described above.
It has a similar structure to the C encoder.

However, the gate circuit 45 encodes only 16 pixel data in the area An+1 on the rear side of one block.

FIG. 8A shows the clock signal P1 supplied to the control signal generation circuit 57. Clock signal P1 is generated at block intervals. From this clock signal P1, as shown in FIG. 8B, a control signal P2 whose level is inverted at a cycle of % of the l block cycle is generated by the control signal generation circuit 57. The period in which the control signal P2 is "0" includes 16 pixel data of the previous area An of one block, and the period in which the control signal P2 is "1" includes 16 pixel data in the subsequent area An+1. It will be done. During the “1” period of the control signal P2, the gate circuit 45 is turned on, and the pixel data of the subsequent area Ar++1 passes through the gate circuit 45 and is supplied to the ADRC encoder 47. A differential pulse P3 shown in FIG. 8C is generated from the differentiating circuit 59 at the timing of the rising edge of the control signal P2. The accumulation circuit 53 is reset by the differential pulse P3 in preparation for the accumulation operation regarding the next block.

The frame dropping process of this embodiment will be explained with reference to FIG. In Fig. 9, F1, F2, F3,...
・represents consecutive first frame, second frame, third frame, etc. As shown in FIG. 9A, one pixel data X1, x2,
Pay attention to X3,... (see Figure 4). An example of changes in the level of these pixel data is shown in FIG. 9B.

The operation when the block of interest, which is the target of frame drop determination, is a block containing pixel data x5 and x6 will be described.

At the timing when pixel data X6 is supplied from input terminal 41, pixel data X2 is generated from four-frame delay circuit 42. Also, at this timing, pixel data X5 is obtained on the output side of the % block delay circuit 43. Therefore, the adder circuit 49 and the bit shift circuit 50 form an interpolated value K(3x6+x2). This interpolated value is subtracted from the pixel data x5 in the subtraction circuit 51. From the subtraction circuit 51, x5%. The subtraction output of (3x6+x2) is obtained. This subtraction output is converted into an absolute value and supplied to the accumulation circuit 53. The accumulation circuit 53 accumulates the absolute value of the subtraction output generated in the area A5 including the pixel data x5. The accumulation period is designated by the period in which the control signal P2 is "1". The accumulated output is compared to a reference value,
When the accumulated value is larger than the reference value, the frame drop flag SJ
is set to "O", and the frame is set to the C1 first mode in which no frame drop processing is performed. That is, 32 from ADRC encoder 46
The encoded output of the transmitted pixel data is output from the switching circuit 4.
8 is selected. A delay of one block occurs between the input data and the output side of the latch 56 where the frame drop flag SJ is generated. On the other hand, in the ADRC encoders 46 and 47, a delay of one block occurs in detecting the maximum value MAX and minimum value MIN of the block. Therefore, the generation of the frame dropping flag SJ and the generation of the encoded output are synchronized.

Contrary to the above, when the accumulated value is smaller than the reference value, the frame drop flag SJ is set to "1", and the second mode is set in which frame drop processing is performed. That is, the 16 transmitted pixel data of area 86 that has passed through the gate circuit 45 is supplied to the ADRC encoder 47, and the encoded output of the ADRC encoder 47 is selected by the switching circuit 48. in this way,
Since the code signal DT of l6 pixels in the area An+1 after one block is transmitted, the transmitted code signal DT
The amount of data can be A.

On the receiving side (playback side), blocks that have not been subjected to frame drop processing are processed by a 3D ADRC decoder.
Restoration values for two pixels are obtained.

On the other hand, regarding blocks that have undergone frame drop processing,
A two-dimensional ADRC decoder obtains restored values for 16 pixels in area An+1. The l6 pixels in the area An that are not transmitted due to frame dropping are in the area A of the same block.
The restoration value at the same position of n+1 and the temporally previous area A n
− Interpolated by linear interpolation with the restored value of the same position of 3.

This interpolation is the same method used when determining whether to drop frames.

d. Modified Example In the above-described embodiment, a flag signal indicating the interpolation method for pixels thinned out by subsampling is generated based on the smallest total error value. However, the number of pixels whose error exceeds a threshold value may be counted, and a flag signal may be generated based on the minimum counted value. Further, if the obtained minimum value exceeds a threshold value, subsampling may not be performed for that block. In this case, it is necessary to add a flag signal regarding subsampling.

Furthermore, in the above-mentioned embodiment, one block is composed of two areas An and An+1 belonging to two frames, respectively,
When frame drop is performed, only the data of the subsequent area A n +1 is transmitted. However, the present invention is not limited to this one embodiment, and it is possible to transmit data of only one arbitrary region among n regions spanning two or more n frames, or transmit data of m (man) regions. may be transmitted.

Further, the present invention can employ an interpolation method other than linear interpolation when determining whether to drop frames. One of them is previous value replacement, in which data in the first area of one block is transmitted, and non-transmitted data in other areas of the same block are held at the same value as the transmitted data. Another example is interpolation of quadratic functions. Furthermore, in the present invention, variable length ADRC may be used. Of course, in the present invention, a high-efficiency code other than ADRC, such as DCT (discrete cosine transform), may be used. However, it is not necessary to perform compression encoding.

〔Effect of the invention〕

This invention combines spatio-temporal subsampling and frame drop processing, so it can significantly increase the compression ratio. In addition, in this invention, since the interpolation method with the smallest error is determined on the transmitting side using the original data, the best interpolation method can be selected correctly compared to selecting the interpolation method from the received data. ．． Furthermore, it is possible to prevent resolution degradation in stationary areas. Furthermore, the present invention obtains an interpolated value using the same method as the interpolation of non-transmitted pixels performed on the receiving side, and determines whether or not to perform frame dropping processing based on the magnitude of the difference between this interpolated value and the original value. It is established. Therefore, even when one of two spatially adjacent blocks is subjected to frame drop processing and the other is not, the difference in luminance level between the two blocks will be small in the restored image, and block distortion will not occur. It can be prevented.

Furthermore, unlike a simple stationary determination, this invention allows frames to be dropped even in areas where level changes occur continuously other than at stationary parts, thereby improving data compression efficiency.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a subsampling and blocking circuit in an embodiment of the invention, and Figs. FIG. 5 is a block diagram of a frame dropping and ADRC encoder in an embodiment of the present invention; FIG. 6 is a block diagram of an example of an ADRC encoder; FIG. 7 is used to explain ADRC. The route map, FIG. 8 is a timing chart used to explain frame dropping and the ADRC encoder, and FIG. 9 is a schematic diagram used to explain frame dropping processing. Explanation of main symbols in the drawings■=Input terminal, 5: Sap sampling and blocking circuit, 6: Frame drop and ADRC encoder, 7: Framing circuit, 24 to 27: Subtraction circuit, 29: Sampling switch, 31: Block 39: Minimum value detection circuit, 42: 4 frame delay circuit, 45: Gate circuit, 46, 47: ADRC encoder, 48: Switching circuit, 5l: Subtraction circuit, 53: Accumulation circuit.

Claims (1)

[Claims] Three frames spanning n frames of a digital television signal.
In a high-efficiency encoding device that thins out a plurality of pixel data contained in a block of 3D by subsampling and transmits the remaining pixel data after the thinning process, the non-transmitted pixel data that is thinned out in each block is For each, a plurality of interpolation methods using temporally and spatially adjacent transmission data are prepared, and for each of the above interpolation methods, a calculation means for calculating the absolute value of the difference between the true value and the interpolated value; means for generating a flag signal representing an optimal interpolation method for each block based on the output; a first mode for transmitting all pixel data for the n frames of each of the subsampled blocks; a second mode in which pixel data for m frames of the frames are transmitted;
From the transmitted pixel data of the frame, (n
m) means for detecting a difference between an interpolated value obtained by interpolating non-transmitted pixel data of a frame and a true value of said non-transmitted pixel data; and a control signal for said switching means regarding said block of interest based on the output of said detecting means. A high-efficiency encoding device comprising: control signal generating means for generating the control signal; and transmission means for transmitting the flag signal, transmission pixel data from the switching means, and the control signal.