JPH031680B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field The present invention relates to a speech synthesis device, and in particular, to a speech synthesis device that has a function of stopping the operation of an oscillation circuit except when vocalization is being performed, in order to reduce the power consumption of the speech synthesis device. The present invention relates to a speech synthesizer.

(b) Background of the Technology Generally speaking, a speech synthesis device stores a plurality of words consisting of a set of speech data in a storage circuit such as a ROM in advance, and when the stored word is selected by a word selection signal, the synthesis is started. When an instructing start signal arrives, speech is synthesized based on the speech data constituting the selected word or phrase. This speech synthesizer operates using a clock signal generated by a built-in oscillation circuit.
If oscillation were to be performed even when a voice synthesis operation was not being performed, power consumption would be large and it would be uneconomical. Normally, power consumption can be reduced by stopping oscillation and then starting oscillation in synchronization with the signal that instructs the start of speech synthesis. However, immediately after oscillation starts, oscillation becomes stable. First, since the frequency changes, there is a risk that the synthesized voice will sound unnatural.

(C) Disclosure of the Invention The present invention has been made in view of the above-mentioned points, and provides an AND signal of at least one of the word selection signals for selecting a plurality of words stored in a storage circuit and a start signal. An oscillation circuit that starts oscillation by the oscillation circuit and a time constant circuit that generates a signal that is delayed by a predetermined time from the start of oscillation of the oscillation circuit are provided, and the reset of the speech synthesis circuit is canceled by the delayed signal of the time constant circuit. By starting the operation of the speech synthesis circuit a predetermined time after the start of oscillation of the oscillation circuit, the influence of unstable oscillation immediately after the start of oscillation is removed, and a speech synthesis device with low power consumption is provided.

(D) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a word selection circuit, 2 is a ROM, 3 is a speech synthesis circuit, 4 is a speaker, 5 is a start control circuit,
6 is an oscillation circuit, and 7 is a time constant circuit.

The word selection circuit 1 receives the applied word selection signal S ₁ ~
When either Sn becomes “H” level,
ROM that stores the words and phrases corresponding to that signal
This specifies the second address. The ROM 2 stores a plurality of phrases constituted by a set of voice data, and outputs the voice data constituting the selected phrase to the voice synthesis circuit 3. The speech synthesis circuit 3 receives the signal output from the start control circuit 5.
Its operation is controlled by the ST, and audio is synthesized based on the applied audio data and is emitted from the speaker 4. The start control circuit 5 outputs the start control signal ST when any one of the applied word selection signals _S1 to Sn becomes "H" level and the applied start signal START becomes "H" level.
is output, instructing the speech synthesis circuit 3 to start the synthesis operation, and setting the R-SFF 8. R-SFF
8 is used as a flag indicating that the speech synthesis circuit 3 is in the midst of synthesis operation, and is reset by the signal END outputted when the synthesis operation is completed.

The oscillation circuit 6 oscillates at a frequency determined by a connected crystal oscillator 9, for example 400 KHz, and creates a clock signal which is the basis of the operation of each circuit, especially the operation of the speech synthesis circuit 3. Also, the oscillation circuit 6
The output CLC of the OR gate 10 controls its oscillation operation and oscillation stop. To the OR gate 10, an OR gate 11 to which word selection signals S ₁ to Sn were applied, an output, and a start signal START were applied.
The output of the ANP gate 12, that is, the word selection signal S ₁
-Sn and the start signal STAMRT, a signal OSCG which is inverted by the inverter 13, and the Q output of the R-SFF8 are applied.

The time constant circuit 7 includes an inverter 14 that inverts the output CLC of the OR gate 10, a C-MOS transistor 15 to which the output of the inverter 14 is applied, an inverter 16 to which the output of the C-MOS transistor 15 is applied, and A resistor 18 is connected between the source of the P-channel MOS transistor of the C-MOS transistor 15 and the power supply _VDD . That is, the signal applied to the gate becomes "L" level,
When the P-channel MOS transistor turns on,
A time constant is formed by the capacitor 17 and the resistor 18, and the input voltage applied to the inverter 16 becomes a voltage that gradually increases according to the time constant. When the threshold voltage of the inverter 16 is reached, the output of the inverter 16 becomes It becomes “L” level. The output of this inverter 16 is applied to the reset terminal R of the speech synthesis circuit 3. Therefore, when the signal CLC becomes "H" level, the output of the inverter 16 changes from "H" level to "L" level after a predetermined time delay, for example, about 10ms to 50ms, by the time constant circuit 7. , the reset of the speech synthesis circuit 3 is released. The delay time of the time constant circuit 7 is set to be slightly larger than the time it takes for the oscillation circuit 6 to oscillate and reach a stable state.

Further, the output of the inverter 16 is applied to the AND gate 19 to which the signal OSCG is applied, and the output of the AND gate 19 is applied to the NOR gate 20 to which the output Q of the R-SFF 8 is applied. The output of NOR gate 20 is output as, and this output
When the speech synthesis device is controlled by a microcomputer, BUSY is used as a signal to determine whether the speech synthesis device is in a state where it can be operated.

Further, the signal is used when the oscillation circuit 6 is forced to start operating from the outside or when the oscillation circuit 6 is kept in a constant oscillation state, and by setting the signal to "L" level, , the output CLC of the OR gate 10 becomes "L" level, and the oscillation circuit 6 starts oscillating.

Next, the operation will be explained with reference to FIG. FIG. 2 is a waveform diagram when vocalization is performed when the signal is at the "H" level and the oscillation circuit 6 has stopped oscillating. First, one of the word selection signals S ₁ to Sn for selecting a word to be uttered,
For example, when the second word is to be uttered, _S2 is set to the "H" level. Then, the word selection signal S ₁ ~
The start signal START is set to the "H" level during a period when either Sn is at the "H" level. When the start control circuit 5 detects that the AND of both has been taken, the start control signal ST pulses to "H".
level. In this case, the start signal START
is set to “H” level in advance, and the word selection signal is
Any one of S ₁ to Sn may be set to "H" level.
The fact that the start control signal ST has become "H" level is stored in the speech synthesis circuit 3, and the start of the speech synthesis operation is instructed, but since the output of the inverter 16 remains at "H" level and is in the reset state. ,
The speech synthesis operation has not started yet. On the other hand, in the OR gate 11 and the AND gate 12, the output of the AND gate 12 is determined by the logical product of the "H" level signal of any of the word selection signals _S1 to Sn and the "H" level of the start signal START. , becomes "H" level, and the output CLC of OR gate 10 becomes "H" level. As a result, the oscillation circuit 6 starts oscillating, but immediately after the oscillation, an abnormal oscillation period in which the frequency is not determined occurs, as shown in FIG. 2 OSC. Further, in synchronization with the start control signal ST going high, R-SFF8 is set and its output Q goes high. Therefore, even if the word selection signals S ₁ -Sn and the start signal START go to "L" level, oscillation is maintained by the R-SFF8. Note that the word selection circuit 1 determines which word has been selected by any of the word selection signals _S1 to Sn.
remembers.

When the output CLC of the OR gate 10 becomes "H" level, the output of the inverter 14 becomes "L" level, and the C-MOS transistor 15
The P-channel MOS transistor is turned on. Therefore, a charging current flows to the capacitor 17 from the power supply _VDD via the resistor 18, and the capacitor 1
7, that is, the input voltage of the inverter 16 gradually increases. When the voltage reaches the threshold voltage of the inverter 16, the inverter 16 is inverted, and the output of the inverter 16 changes from the "H" level to the "L" level. At this time, the abnormal oscillation of the oscillation circuit 6 has already disappeared and stable oscillation is being performed. Therefore, the output of the inverter 16 is "L"
Since the reset of the speech synthesis circuit 3 is canceled by reaching the level, the speech synthesis circuit 3 starts the synthesis operation and selects the words addressed by the word selection circuit 1.
The audio is transmitted to speaker 4 based on the audio data in ROM2.
Be more vocal.

In this manner, the speech synthesis circuit 3 can be operated after the oscillation circuit 6 has achieved sufficiently stable oscillation. When the speech synthesis circuit 3 finishes uttering the selected word, the speech synthesis circuit 3 sets the end signal END to the "H" level and resets the R-SFF8. As a result, the output Q goes to the "L" level, so the output CLC of the OR gate 10 goes to the "L" level.
level, and the oscillation of the oscillation circuit 6 stops. Therefore, since oscillation is stopped except during voice production, power consumption can be saved.

(E) Effects As described above, according to the present invention, the oscillation of the oscillation circuit is stopped except during voice production, and the oscillation is started by the AND signal of the word selection signal and the start signal, and the time constant circuit By canceling the reset of the voice synthesis circuit after a predetermined time delay from the start of oscillation, power consumption can be significantly reduced and the influence of abnormal oscillation immediately after the start of oscillation can be completely eliminated. Therefore, there is an advantage that the quality of the speech synthesis device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram explaining the operation of the embodiment shown in FIG. Explanation of main figure numbers, 1...word selection circuit, 2...
ROM, 3...speech synthesizer, 4...speaker, 5...
Start control signal, 6...Oscillation circuit, 7...Time constant circuit.

Claims (1)

[Claims] 1. a speech synthesis circuit that utters a word selected by a plurality of word selection signals based on audio data; a start control circuit to which the word selection signal and a start signal are applied and controls the start of synthesis of the speech synthesis circuit; an oscillation circuit whose start of operation is controlled by an AND signal of at least one of the plurality of word selection signals and the start signal, and which creates a clock signal that is the basis of the operation of each circuit; and a time constant circuit that outputs a signal delayed by a predetermined time from the start of oscillation of the circuit, and the reset of the speech synthesis circuit is canceled by the signal delayed by the predetermined time and the speech synthesis operation is started. Synthesizer.