JPH03178128A - Manufacture of iii-v compound semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to improve the characteristics of the title device and the yield of the manufacture of the device by a method wherein at least an ion-implantation is performed in the exposed surface of a III-V compound semiconductor layer for suppressing leaving of arsenic from the layer. CONSTITUTION:A GaAs layer 2 of a composition containing excessively As and a GaAs layer 3 of normal composition are grown on a semiinsulative GaAs substrate 1 in a thickness of 5000Angstrom and a thickness of 1500Angstrom by a molecular beam crystal growth method. Then, n<+> regions 4 to be used for a source and a drain are formed by implanting Si using a Schottky gate electrode 5 consisting of WSi as a mask. Then, an etching is performed up to a depth to reach the layer 2 using a photoresist film 6 as a mask leaving an operating layer of a field-effect transistor and an interelement isolation is performed. Then, oxygen is implanted using the film 6 as a mask, then, after the film 6 is removed, an annealing and the formation of ohmic electrodes on the regions 4 are performed. In such a way, as leaving of the arsenic is prevented by performing an ion-implantation, the improvement of the characteristics of a device and the improvement of the yield of the manufacture of the device are contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a ■-v group compound semiconductor device having a ■-v group compound semiconductor layer containing excessive arsenic.

[Conventional technology]

■-V group compound semiconductors with an excess of arsenic compared to their stoichiometric composition can obtain higher resistivity than usual, and are useful for reducing interelement interference effects in semiconductor integrated circuits and for field effect transistors with fine gates. It can be used to improve the performance of semiconductor devices, such as improving the current confinement effect. A -V group compound semiconductor containing excess arsenic can be obtained by growing a crystal using a molecular beam crystal growth method at a temperature lower than the growth temperature at which a stoichiometric composition is obtained.

However, in a group I[IV compound semiconductor crystal containing excessive arsenic, arsenic is easily desorbed and deterioration of device characteristics is likely to occur in the semiconductor device manufacturing process, particularly in the heat treatment process, and the yield is low. In order to avoid such problems, restrictions have been placed on the device structure and manufacturing process, such as not exposing an excess layer of arsenic to the surface or lowering the maximum processing temperature.

[Problem to be solved by the invention]

In the process of manufacturing semiconductor devices using a substrate having a ■-V group compound semiconductor layer containing excessive arsenic, conventional measures to prevent the release of arsenic have been incomplete. In the case where it was not exposed to the surface, the deterioration of device characteristics due to the effect of arsenic desorption was reduced, but not completely eliminated. Furthermore, when the maximum processing temperature is lowered, a problem arises in that device characteristics deteriorate due to deterioration of ohmic electrode characteristics, even if the effect of arsenic desorption can be ignored.

The purpose of the present invention is to: In the manufacturing process of a semiconductor element on a substrate having a ■-V group compound semiconductor layer containing excessive arsenic,
It is an object of the present invention to provide a method for manufacturing a III-V compound semiconductor device in which desorption of arsenic is suppressed without deterioration of device characteristics by implanting ions into a substrate, and the characteristics and yield are improved.

[Means to solve the problem]

The method for manufacturing a group IV compound semiconductor device of the present invention includes the method for manufacturing a group IV compound semiconductor device in which a semiconductor element is formed on a substrate having a group group IV compound semiconductor layer containing excessive arsenic. (1) Ions are implanted into at least the exposed surface of the (1)-V group compound semiconductor layer in order to suppress desorption of arsenic from the (1)-V group compound semiconductor layer.

[Operation] GaAs containing excess arsenic compared to the stoichiometric composition was created using the molecular beam crystal growth method and grown at 900°C for 50 minutes in a nitrogen atmosphere.
When annealing is performed for a second, group II metal particles are observed due to the elimination of arsenic. This is because arsenic microcrystals with a diameter of approximately 5 OA are present in the ■-V group arsenic compound semiconductor layer that contains excess arsenic compared to the stoichiometric ratio, and in the arsenic crystal, group ■ elements and This is because arsenic is more easily desorbed than in a bonded state, so desorption is more likely to occur in the microcrystalline portion during heat treatment. When a similar experiment was carried out after ion implantation into the sample, no grains of group III metal were observed, indicating that the desorption of arsenic was suppressed. The reason why desorption of arsenic is suppressed is considered to be that when ion implantation is performed into an arsenic-excessive layer, arsenic microcrystals are fragmented and bonding with group Ⅰ elements increases.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention, and particularly show the case where the present invention is applied to a field effect transistor.

As shown in FIG. 1(a), a GaAs layer 2 with an excessive arsenic composition was grown at 500 OA on a semi-insulating Ga AJ substrate 1, and a GaAs layer 3 with a normal composition was grown at 150 OA by molecular beam crystal growth. The growth temperature was 200°C for GaAs layer 2;
In the As layer 3, the temperature is 600°C. The GaAs layer 3 is doped with Si to make it an n-type of lx1017 cm-3.

Next, as shown in FIG. 1(b), the n+ regions 4 used for the source and drain are formed by implanting 5xlO''cm<-2> of Si at an energy of 100 keV using the Schottky gate electrode 5 made of WSi as a mask. Next, using the photoresist film 6 as a mask, etching is performed to a depth that reaches the GaAs layer 2, leaving the active layer of the field effect transistor, to isolate devices.Next, an annealing step is required to activate the n+ region 4. However, as it is, Ga with excessive arsenic composition
Since arsenic is desorbed from the As layer 2, using the photoresist film 6 as a mask, oxygen is irradiated with 1xlO at an energy of 80 keV.
After removing the photoresist film 6, annealing is performed at 900° C. and an ohmic electrode is formed on the n+ region 4, thereby completing the manufacturing process.

As a result of integrating the field effect transistor formed in this way, deterioration in device characteristics and yield caused by the introduction of the GaAs layer 2 with an excessive arsenic composition did not occur. This is because desorption of arsenic from the GaAs layer 2, which has an excessive arsenic composition, can be suppressed by implanting oxygen ions into the isolation region. In addition, by introducing the GaAs layer 2 with an excessive arsenic composition and suppressing arsenic desorption, the inter-element interference effect can be stably reduced, and the distance between elements can be reduced from the conventional 10 μm to 3 μm.
We were able to reduce it to m.

The above example is an example of manufacturing a Schottky gate field effect transistor using GaAs, but the I
-If the structure has a V group compound semiconductor layer, InG
Even if the aAsGaAs layer 2 material is used, the present invention can basically be applied to any semiconductor device having any structure.

Furthermore, in this example, oxygen ions were implanted into the GaAs layer 2 containing excess arsenic, but if appropriate implantation energy and dose are selected, ions of other atoms such as B or molecules such as BP and + can be implanted. You can.

Furthermore, in this example, all the wafer structures necessary for semiconductor device fabrication were created using the molecular beam crystal growth method.
The layers other than the As layer 2 may be formed by other methods such as metal organic vapor phase epitaxy.

〔Effect of the invention〕

As explained above, the present invention is directed to ■-V containing excessive arsenic.
By performing ion implantation to prevent arsenic desorption in the process of manufacturing semiconductor devices using a substrate having a group compound semiconductor layer, arsenic desorption is eliminated, improving yields and improving device structure and manufacturing. The degree of freedom in the process is increased, and it is possible to design and manufacture a semiconductor device that can effectively utilize the high resistivity of the -V group compound semiconductor layer containing excess arsenic.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention. 1...GaAs substrate, 2...GaAs with excessive arsenic
layer, 3...GaAs layer, 4...n4' region, 5...
・Schottky gate electrode, 6... photoresist film,
7...Oxygen injection region.

Claims (1)

[Claims] In a method for manufacturing a III-V compound semiconductor device in which a semiconductor element is formed on a substrate having a III-V compound semiconductor layer containing excessive arsenic, desorption of arsenic from the III-V compound semiconductor layer is suppressed. At least this III−
1. A method for manufacturing a III-V compound semiconductor device, which comprises performing ion implantation into an exposed surface of a group V compound semiconductor layer.