JPH0449627A - Manufacture of compound semiconductor device - Google Patents

Manufacture of compound semiconductor device

Info

Publication number
JPH0449627A
JPH0449627A JP16020490A JP16020490A JPH0449627A JP H0449627 A JPH0449627 A JP H0449627A JP 16020490 A JP16020490 A JP 16020490A JP 16020490 A JP16020490 A JP 16020490A JP H0449627 A JPH0449627 A JP H0449627A
Authority
JP
Japan
Prior art keywords
forming
effect
insulation layer
semiconductor device
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16020490A
Other languages
Japanese (ja)
Inventor
Mikio Kanamori
金森 幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16020490A priority Critical patent/JPH0449627A/en
Publication of JPH0449627A publication Critical patent/JPH0449627A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To enable back-crate effect and side-crate effect to be reduced by forming an insulation layer below an operation layer. CONSTITUTION:Boron is implanted into an entire surface of a semiinsulation compound substrate 1 by the ion-implantation method for forming an insulation layer 6. After that, silicon is implanted selectively, heat treatment is performed, and an operation amount (n) 4 is formed. Crystal defect which is generated when forming the insulation layer 6 can be recovered to some extent but crystal defect remains in a region of the insulation layer 6 which is 0.3mum to 0.5mum deep from a surface of the semi-insulation compound substrate 1, and this presence restricts back gate effect. Then, a Schottky gate electrode 1, a source electrode 2, and a drain electrode 3 are formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a compound semiconductor device.

〔従来の技術〕[Conventional technology]

従来この種の化合物半導体装置、特に電界効果トランジ
スタ(FET)は、第2図に示す断面模式図のように、
半絶縁性化合物基板1表面に形成された動作層(n層)
4と、ショットキーゲート電極1と、オーミック性のソ
ース電極2.およびドレイン電極3とから構成されてい
る。近年、このようなFETを用いた集積回路の実用化
、製品化が進められている。
Conventionally, this type of compound semiconductor device, especially a field effect transistor (FET), has a structure as shown in the cross-sectional schematic diagram in FIG.
Operating layer (n layer) formed on the surface of the semi-insulating compound substrate 1
4, a Schottky gate electrode 1, and an ohmic source electrode 2. and a drain electrode 3. In recent years, integrated circuits using such FETs have been put into practical use and commercialized.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述のFETの場合、いわゆるバックゲート効果が問題
となり、このFETと隣接するFETのサイドゲート電
極7との間に第2図に示したような電位が印加されたと
き、バックゲート効果はサイドゲート効果としてあられ
れる。これはサイドゲート電極7の電圧印加により隣接
FETの特性変動、特にドレイン電流が減少する現象で
ある。
In the case of the FET mentioned above, the so-called back gate effect becomes a problem, and when a potential as shown in FIG. 2 is applied between this FET and the side gate electrode 7 of the adjacent FET, the back gate effect It will rain as an effect. This is a phenomenon in which characteristic fluctuations of adjacent FETs, particularly drain currents, decrease due to voltage application to the side gate electrode 7.

この場合には動作層(n層)4の下の半絶縁性化合物基
板1の電位が変動するために発生するものである、この
バックゲート効果により、集積回路が異常動作すること
になり、このため、集積度を上る妨げになっている。
In this case, the back gate effect, which occurs due to fluctuations in the potential of the semi-insulating compound substrate 1 under the active layer (n layer) 4, causes the integrated circuit to operate abnormally. This is an obstacle to increasing the degree of integration.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の化合物半導体装置の製造方法は、半絶縁性化合
物基板の表面にイオン注入法1例えばボロンあるいはプ
ロトンあるいは酸素をイオン注入することにより動作層
形成領域より深い位置1例えば0.3μmから0.5μ
mの深さに絶縁層を形成し、前記絶縁層上に動作層を形
成し、化合物半導体装置を形成する工程を有している。
The method for manufacturing a compound semiconductor device of the present invention involves implanting ions, for example, boron, protons, or oxygen, into the surface of a semi-insulating compound substrate at a position deeper than the active layer formation region, for example, from 0.3 μm to 0.3 μm. 5μ
The method includes the steps of forming an insulating layer to a depth of m, forming an active layer on the insulating layer, and forming a compound semiconductor device.

〔実施例〕〔Example〕

第1図(a)、(b)は本発明の一実施例を説明するた
めの断面図である。
FIGS. 1(a) and 1(b) are sectional views for explaining one embodiment of the present invention.

まず、第1図(a)に示すように、半絶縁性化合物基板
1の表面全面に、イオン注入法でボロンを150keV
でI X 1013c m−”の条件で注入し、絶縁層
6を形成する。
First, as shown in FIG. 1(a), boron was injected at 150 keV onto the entire surface of a semi-insulating compound substrate 1 by ion implantation.
The insulating layer 6 is formed by implanting under the condition of I x 1013 cm-''.

その後、第1図(b)に示すように、シリコンを選択的
に注入し、800℃程度で熱処理を行ない、動作層(n
)4を形成する。この熱処理により、さきの絶縁層6を
形成する際に生じた結晶欠陥はある程度回復するが、半
絶縁性化合物基板1の表面から0.3μmから0.5μ
mの深さの絶縁層6の領域では結晶欠陥が残り、これの
存在によりバックゲート効果を抑制することができる。
Thereafter, as shown in FIG. 1(b), silicon is selectively implanted and heat treated at about 800°C to form an active layer (n
) form 4. Through this heat treatment, crystal defects that occurred during the previous formation of the insulating layer 6 are recovered to some extent, but the temperature is 0.3 μm to 0.5 μm from the surface of the semi-insulating compound substrate 1.
Crystal defects remain in the region of the insulating layer 6 with a depth of m, and the presence of these defects can suppress the back gate effect.

続いて、ショットキーゲート電極1.ソース電極2.ド
レイン電極3を形成することにより、FETの製造が完
了する。
Next, Schottky gate electrode 1. Source electrode 2. By forming the drain electrode 3, the manufacture of the FET is completed.

本実施例では絶縁層6の形成のイオン注入にボロンを用
いたが、プロトンあるいは酸素のイオン注入を用いても
よい。
In this embodiment, boron was used for ion implantation to form the insulating layer 6, but proton or oxygen ion implantation may also be used.

なお、本実施例では動作層4を形成する前に絶縁層6を
形成した。逆に、動作層4を形成した後に絶縁層6を形
成すると、これの形成後には熱処理が行なわれないため
、バックゲート効果は大きく抑制される。しかしながら
、動作層4には結晶欠陥が多数形成され、FET特性1
例えば相互コンダクタンスの低下を招くことになる。
Note that in this example, the insulating layer 6 was formed before forming the active layer 4. Conversely, if the insulating layer 6 is formed after the active layer 4 is formed, no heat treatment is performed after the formation of the insulating layer 6, so that the back gate effect is greatly suppressed. However, many crystal defects are formed in the active layer 4, and the FET characteristics 1
For example, this results in a decrease in mutual conductance.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、動作層の下に絶縁層を形
成することにより、バックゲート効果。
As explained above, the present invention eliminates the back gate effect by forming an insulating layer under the active layer.

サイドゲート効果を低減することができる。Side gate effects can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は本発明の一実施例を説明すうた
めの断面図、第2図は従来の技術を説明するための断面
模式図である。 1・・・ショットキーゲート電極、2・・・ソース電極
、3・・・ドレイン電極、4・・・動作層、5・・・半
絶縁性化合物基板、6・・・絶縁層、7・・・サイドゲ
ート電極。
FIGS. 1(a) and 1(b) are cross-sectional views for explaining an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view for explaining a conventional technique. DESCRIPTION OF SYMBOLS 1... Schottky gate electrode, 2... Source electrode, 3... Drain electrode, 4... Operating layer, 5... Semi-insulating compound substrate, 6... Insulating layer, 7...・Side gate electrode.

Claims (1)

【特許請求の範囲】 1、半絶縁性化合物基板の表面にイオン注入法により動
作層形成領域より深い位置に絶縁層を形成し、前記絶縁
層上に動作層を形成し、化合物半導体装置を形成するこ
とを特徴とする化合物半導体装置の製造方法。 2、請求項1記載の化合物半導体装置の製造方法におい
て、イオン注入法がボロン、あるいはプロトン、あるい
は酸素をイオン注入する方法であることを特徴とする化
合物半導体装置の製造方法。
[Claims] 1. An insulating layer is formed on the surface of a semi-insulating compound substrate at a position deeper than an active layer formation region by ion implantation, an active layer is formed on the insulating layer, and a compound semiconductor device is formed. A method for manufacturing a compound semiconductor device, characterized in that: 2. The method of manufacturing a compound semiconductor device according to claim 1, wherein the ion implantation method is a method of implanting boron, protons, or oxygen ions.
JP16020490A 1990-06-19 1990-06-19 Manufacture of compound semiconductor device Pending JPH0449627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16020490A JPH0449627A (en) 1990-06-19 1990-06-19 Manufacture of compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16020490A JPH0449627A (en) 1990-06-19 1990-06-19 Manufacture of compound semiconductor device

Publications (1)

Publication Number Publication Date
JPH0449627A true JPH0449627A (en) 1992-02-19

Family

ID=15710033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16020490A Pending JPH0449627A (en) 1990-06-19 1990-06-19 Manufacture of compound semiconductor device

Country Status (1)

Country Link
JP (1) JPH0449627A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420775B1 (en) 1996-02-29 2002-07-16 Nec Corporation Compound semiconductor device having an ion implanted defect-rich layer for improved backgate effect suppression

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420775B1 (en) 1996-02-29 2002-07-16 Nec Corporation Compound semiconductor device having an ion implanted defect-rich layer for improved backgate effect suppression

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