JPH031789A - Synchronizing signal reproducing circuit - Google Patents

Abstract

PURPOSE:To prevent the system clock from being fluctuated depending on the content of a picture by using a line burst signal not subjected to the effect of ghost as a reference signal for generating a system clock. CONSTITUTION:A switch Sw2 is switched selectively with a signal from a latch circuit 20 being a means detecting whether or not an input signal is normal. A burst gate pulse (non signal line and a line burst gate succeeding to a fixed signal line such as VITS or the like) appears by a synchronizing signal pulse reproducing device 19 at a normal input via the switch Sw2 and a switch Sw1 is turned to the contact (a). A burst signal of the succeeding line to the fixed signal such as VITS or the like and a non signal line is supplied among outputs of a BPF 11 is fed to a PLL oscillation circuit 16 to lock the burst of the line not subjected with the effect of ghost. Thus, the synchronizing signal is not moved unstably together with the change in the video image.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synchronization signal reproducing circuit, and is particularly applicable to various video equipment such as a TV receiver that handles TV (television) video signals, and to such video equipment. applied goth 1-removal;
The present invention also relates to a synchronization signal regeneration circuit that can be applied to a waveform distortion removal device.

[Conventional technology]

A conventional synchronizing signal reproducing circuit will be explained with reference to FIG. FIG. 2 is a block diagram of a conventional synchronization signal reproducing circuit 1, and 11 is a center frequency of 3.58M1lz.
12 is a composite synchronization signal separation circuit (Sync, 5epa, ), 13 is a horizontal synchronization signal separation port rI? I(It 5ync, 5epa, ), 1
4 is a vertical synchronization signal separation circuit (V 5ync, 5epa,
), 15 is a burst gate pulse generator (Burst
Gate Pulse Gen, ), 16 is P L
L (Phase Locked LOOD) oscillation circuit, 17 is horizontal/vertical synchronization signal regenerator ftl, V 5y
nc, Regener-ator). The burst gate pulse generator 15 is composed of a monostable multivibrator (mono-multi), etc., and the PLLQ oscillator circuit 16 is composed of a phase detector 1 low 14f (wavelength generator (LPr), an '8 pressure control oscillator <
V CO: Voltage Control (l
The horizontal/vertical synchronizing signal regenerator 17 is composed of a counter ROM, a latch, a gate element, etc.

The input video signal coming from the human power line 11 is B P
F 11 , composite synchronization signal separation port i? 812. Horizontal synchronization signal separation port U@13 and vertical synchronization signal separation circuit 1
11, and from each circuit, a color subcarrier (Co1or 5ub-carrier) of 3.58M11Z,
A composite synchronization signal, a horizontal synchronization signal, and a vertical synchronization signal are separated and output. The pulse 1 to gate pulse generator 15 receives the composite synchronization signal from the composite synchronization 1 signal separation circuit 12, and based on this, generates a gate pulse for not extracting the burst portion of each horizontal scanning line period. and outputs it to switch Swl. The switch SvI is switched to the contact a side when this gate pulse is generated, and the burst number G-J of each line out of the output of the B r"F 11 is supplied to the PL l-oscillation circuit 17816. Using the burst signal as a reference, in the PLL oscillation circuit 16, the synchronization signal regeneration cycle II
? A reference signal that controls the entire system including 11 (
For example, in the case of a digital system, a system clock used as a sampling clock, etc. is generated. P
The output signal of the LL oscillation circuit 16 is output via the output line 12 as a reference signal such as a system clock, and is also supplied to the horizontal/vertical synchronizing signal regenerator 17.

The horizontal/vertical synchronization signal regenerator 17 is also supplied with the horizontal synchronization signal from the horizontal synchronization signal separation circuit 13 and the vertical synchronization signal from the vertical synchronization signal separation circuit 14. Horizontal and vertical synchronization signals suitable for the system are regenerated and output via output lines 13 and 14, respectively.

As described above, a burst signal for each line (horizontal scanning line) is used as a reference signal for generating a system clock that serves as a reference for the entire system.

[Problem to be solved by the invention]

In the conventional synchronization signal reproducing circuit 1 as described above, when the video signal is affected by ghosts, the burst of the video period is covered by the ghost portion of the video signal of the previous line, so the video movement is affected. Therefore, the synchronization signal reproduced from the gated burst also moves unstablely as the video changes.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a band-wave device, a composite signal generator, and a composite signal generator for separating and outputting a color subcarrier, a composite synchronization signal, a horizontal synchronization signal, and a vertical synchronization signal, respectively, from a color composite video signal that is an input signal. A gate for extracting the parts 1 to 1 of each horizontal scanning line period based on the composite synchronization signal from the synchronization signal separation circuit, the horizontal synchronization signal separation circuit, the vertical synchronization signal separation circuit, and the composite synchronization signal separation circuit. A pulse 1 to gate pulse generator that generates pulses, a PLL oscillation circuit that generates a reference signal that controls the entire system based on the burst signal of each line from a bandpass filter, and this PLL oscillation circuit. Reference signal and horizontal synchronization signal separation circuit from the nameplate, horizontal synchronization signal from the vertical synchronization signal separation circuit,
A horizontal/vertical synchronizing signal burst gate pulse regenerator that inputs a vertical synchronizing signal and generates a reproduced horizontal synchronizing signal, a reproduced vertical synchronizing signal, and a burst gate pulse based on these signals, and this horizontal/vertical synchronizing signal burst. Detection means for inputting the reproduced vertical synchronization signal from the gate pulse regenerator and the vertical synchronization signal from the vertical synchronization signal separation circuit and determining whether or not the input video signal is normal based on both signals; When it is determined that a normal video signal is input based on the detection result by the means, the period in which there is no video signal within the vertical blanking period and the perspective l of the horizontal scanning line following the period of the fixed signal are -Horizontal/vertical synchronization signal burst that gates only the signal.The gate circuit in the gate pulse regenerator extracts the gate pulse and regenerates the synchronization signal from this pulse. When it is determined that no signal is being input, the synchronization signal is reproduced from the burst gate pulse from the burst gate pulse generator that gates the burst signals of all periods of the input video signal.

〔Example〕

An embodiment of the synchronizing signal reproducing circuit of the present invention will be described with reference to FIG. 1 and subsequent figures. FIG. 1 is a block diagram of a synchronization signal reproducing circuit 10 according to the present invention. In this figure, the same components as those in the conventional example shown in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted. In the figure, 20 is a latch circuit which is a means for detecting whether the input signal is normal or not;
19 is a horizontal/vertical synchronizing signal burst gate pulse regenerator (hereinafter also simply referred to as [synchronizing signal/pulse regenerator J)]
It is.

The human input e1 word from input line C1 is BPF'11
, composite synchronization signal separation circuit 12. Horizontal synchronization signal distribution circuit 1
3. and a vertical synchronization signal separation circuit 14, and each circuit separates and outputs a 3.58M11z color subcarrier, a composite synchronization signal, a horizontal synchronization signal 1, and a vertical synchronization signal. The burst gate pulse generator 15 inputs the above-mentioned composite synchronization signal, generates a gate pulse for not extracting the burst portion for each horizontal scanning line period based on the signal, and switches S
Output to contact C side of %v2. Contact d of switch Sw2
On the side, there is a no-signal line generated by the synchronization signal/pulse regenerator 19 and a VITS (Vertical Inter
A burst gate pulse is supplied that gates only the next line (horizontal scanning line) of the fixed signal line, such as val Te5t Signal, for a burst period. This switch SW2 is selectively switched depending on the result of determination as to whether or not the signal from the latch circuit 20, that is, the video signal, is normal.

Determination as to whether the video signal is normal or abnormal is made by latching the vertical synchronizing signal from the vertical synchronizing signal separation circuit 14 at the edge of the vertical synchronizing signal reproduced by one synchronizing signal/pulse regenerator. The principle of operation will be explained with reference to the signal waveform diagram in FIG.

Figure 3 is a schematic diagram (timing chart) of each vertical synchronization signal.The reproduced vertical synchronization signal is
Since it can be set to any timing according to the application, taking into account the delay time caused by the vertical synchronization signal separation circuit 14,
As shown in FIG. 3(C), the rising point is set in advance to be in the middle of the negative polarity vertical synchronization pulse which is the output signal of the vertical synchronization signal separation circuit 14. As a result, L (Low 1evel) is latched during normal input, and l-1 (thigh 1evel) is latched during abnormal input.
is latched and supplied to the latch circuit 20. As a result, a burst gate pulse from the synchronizing signal/pulse regenerator 19 (burst gate only for the no-signal line and the line next to the fixed signal line such as VITS) appears from the switch SW2 during normal input, and during abnormal input. , a pulse 1 to gate pulse (burst gate of each line) from the burst gate pulse generator 15 appears.

The burst gate pulse output from the switch 51v2 causes the switch Swl to switch to the contact a side.
available. That is, the PLL oscillation circuit 16 has 13PFi
Among the outputs of l, during normal input, no signal line and VIT
The burst signal of only the next line of the fixed signal line such as S is supplied, and in the event of an abnormal input, it is supplied to the in-line burst L-(MU or PLL) and the oscillation circuit 16.The principle of operation is explained in FIG. This will be explained along with a signal waveform diagram (timing chart).

FIG. 4(8) is a schematic diagram of signals around the vertical blanking period. (8) in the same figure shows the burst gate pulse signal (
(corresponds to the output of the burst gate pulse generator 15). In this case, n lines of bursts are extracted, but if the input signal has ghost 1~, the ghost component of the signal of one line will overlap with the burst of the next line. Since a signal that fluctuates over time, such as the ghost component, naturally fluctuates accordingly, the extracted burst also fluctuates.

On the other hand, in the no-signal (black burst) line immediately after the vertical synchronization signal or the line next to the fixed signal line such as VITS, the ghost component also becomes a fixed signal, so the first
When a burst is extracted by inputting the burst gate pulse used during normal input to the circuit of the present invention as shown in FIG. fc), the extracted burst does not fluctuate.

Based on the burst signal extracted in this way,
In the PLLq oscillator circuit 16, a reference signal (for example, a system clock used as a sampling clock in the case of a digital system) for controlling the entire system including the circuit 10 of the present invention is generated. The output signal of the PLL oscillation circuit 16 is outputted via the output line 12 as a reference signal such as a system clock, and is also supplied to the synchronization signal/pulse regenerator 19. The horizontal synchronization signal from the horizontal synchronization signal separation circuit 3 and the vertical synchronization signal from the vertical synchronization signal fairness circuits 1 and 1 are similarly supplied to one of the synchronization signal/pulse regenerators. Water and vertical synchronization signals suitable for the system are regenerated from each signal and outputted via output lines i3 and I14, respectively.

FIG. 5 is a block diagram showing a more specific example of the configuration of one synchronizing signal/pulse regenerator. As shown in this figure, the synchronizing signal/pulse regenerator 19 includes child circuits 21 to 24 . Counter 25-26. Gate element (NAND circuit>27~
29. and RoM3o.

31 etc., and these are connected as shown in the figure.

A system clock signal supplied from the PLL oscillation circuit 16 via the input line e5 is supplied to the counter 25 as a count clock, and is also supplied to launch circuits (inverting latches) 21 and 22. The circuit consisting of these latch circuits 21 and 22 and the WAND circuit llI27 is connected to the horizontal synchronizing signal separation interval 1i! Input line β from 813
6 is converted into a 1-clock width reset signal, and the HAND circuit 27 converts the horizontal synchronization signal supplied through counter
Output to the reset input terminal of 5. Therefore, counter 2
5 is reset every line and incremented every 120 lines.
0 will be given the count number of black and y-rolls in one line. Specifically, the clock frequency is 4 f
sc (every 14.3 MIIz), one line is 910 clocks. A clock-by-clock timing signal within the range of one line is stored in the ROM 30 in advance, and a reproduced horizontal synchronization signal is output from the output line β3 in accordance with the timing signal, and a burst signal is output to the HAND circuit 29. A gate pulse (see FIG. 4(B)) is output.

The horizontal synchronization signal supplied from the horizontal synchronization signal separation circuit 13 via the input line 16 is also supplied to the counter 26 as a count clock, and is also supplied to the latch circuit (inversion latch) 23 and the latch circuit <IF inversion latch. )
24 is also supplied. The circuit consisting of these latch circuits 23 and 24 and the NAN [ ] circuit 28 converts the vertical synchronization signal supplied from the vertical synchronization signal separation circuit 13 via the input line 17 into a one-line width reset signal, and
The circuit 28 outputs the signal to the reset input terminal of the counter 26.

Therefore, the counter 26 is reset every field and incremented every l line, and the count number of lines in one field is given from the counter 26 to the ROM 31.

A timing signal for each line within the range of one field is stored in advance in the ROM 31, and a reproduced vertical synchronization signal is output from the output line 14 accordingly, and a black burst signal is output to the two NAND circuits. Ya VI
A burst gate line pulse is output that extracts only the next line of a fixed signal such as TS (negative polarity in the configuration shown in this figure). The NANO circuit 29 combines one burst gate word for each line from the ROM 30 with a burst gate line pulse from the ROM 31 representing the line from which the burst should be extracted, and generates a black burst or VITS signal.
A burst gate pulse that gates only the burst portion of the next line of fixed f8 is generated and output to contact d of switch Sv2 (see FIG. 1).

By setting the contents of ROM 30 and 31 in advance in this way, it is possible to generate necessary timing signals in addition to horizontal and vertical synchronizing signals and burst gate pulses at any timing within one field. can. Further, the reproduced vertical synchronization signal outputted from the ROM 31 via the output line 14 is also used as a clock signal for the launch circuit 20 in FIG.

Next, the operation of the synchronization signal reproducing circuit 10 of the present invention during a transient phenomenon from a normal input to an abnormal input, or vice versa, will be explained with reference to FIGS. 3 and 4. . If the normal input state changes to an abnormal input state where the input video signal disappears or is greatly disturbed,
First, as explained in FIG. 3, the judgment result of the latch circuit 20 detects an abnormal input state and switches the switch Sv2 to contact C.
switch to the side to generate a system clock using a burst signal for each line. At this time, since the input video signal is actually greatly disturbed or does not exist, the PLl-oscillation circuit 16 enters a free run state in which it oscillates at a frequency close to the original system clock frequency. Also, since the horizontal synchronization signal and vertical synchronization signal from the horizontal synchronization signal separation circuit 13 and the vertical synchronization signal separation circuit 14 are also eliminated, the counters 25 and 26 in the synchronization signal/pulse regenerator 19 are no longer reset, and the reproduced horizontal synchronization signal And the reproduced vertical synchronization signal outputs pulses at a period different from the original period. This state can be said to be a state of waiting for normal input.

Next, when transitioning from an abnormal input state to a normal input state, such as when the device main body is powered on at 08:00, the composite synchronizing signal separation circuit 12 starts to operate normally, and the burst signal for each line is The system clock generation by the system clock is now locked to the burst signal even though it is affected by the ghost. Furthermore, since the outputs of the horizontal synchronizing signal separation circuit 13 and the vertical synchronizing signal separation circuit 14 return to normal, the counters 25 and 26 in the synchronizing signal/pulse regenerator 19 are also reset at the original period. As a result, the reproduced vertical synchronization signal is also generated at the original period (timing), so when the judgment result of the latch circuit 20 detects a normal input state, the switch Sv2 is switched to the contact d side, and the synchronization signal/pulse regenerator 19 generates the signal. The system clock generation is returned to the system clock generated by the burst during the burst gate pulse period, and the operation returns to the normal input state.

As mentioned above, after determining whether the input is normal or not, the burst signal of the line that is not affected by ghosts is used as the reference signal for system blackout, which becomes the reference for the entire system when the input is normal. It is.

〔effect〕

As described above, the synchronization signal reproducing circuit of the present invention is configured to conveniently use one burst word of a line that is not affected by ghosts as a reference signal for system clock generation. However, it is possible to prevent the system clock from fluctuating depending on the content of the image. In addition, the vertical synchronization signal separated from the video signal is latched using the reproduced vertical synchronization signal to determine whether the input is normal or not, and system clock generation using the burst l-signal for each line even in the event of abnormal human power. Therefore, even when transitioning from an abnormal input state to a normal input state, such as at 08:00 when the main unit of the device that employs the circuit of the present invention is powered on, each line (
The system clocks the burst signal of each line) and then locks to the burst signal of the line that is not affected by ghosting, so it is reliable.
Moreover, the circuit configuration has practical features such as being able to be realized by only making slight additions or changes to the conventional circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the synchronization signal regeneration circuit of the present invention, and FIG.
The figure is a block diagram of the conventional circuit, Figures 3 and 4 are signal waveform diagrams (timing charts) for explaining the operation of the conventional circuit and the circuit of the present invention, and Figure 5 is a specific block diagram of the main parts of the circuit of the present invention. It is. 10... Synchronous signal regeneration circuit, 11... Bandpass filter,
12...Composite synchronization signal separation circuit, 13...Horizontal synchronization signal separation circuit, 14...Vertical synchronization signal separation circuit, 15
...burst gate pulse generator, 16...PLL
Oscillation circuit, 1...horizontal/vertical synchronization signal burst game
1-pulse regenerator, 20-24... latch circuit, 25
゜26...Counter, 27-29...Gate element,
3゜31-ROM, 5Nvl, 5W2-2. Patent applicant: Kunio Tadashi, representative of Victor Japan Co., Ltd.

Claims (1)

[Claims] A bandpass filter, a composite synchronization signal separation circuit, and a horizontal synchronization signal that separate and output a color subcarrier, a composite synchronization signal, a horizontal synchronization signal, and a vertical synchronization signal from a color composite video signal that is an input signal. Burst gate pulse generation that generates a gate pulse for not extracting the burst portion of each horizontal scanning line period based on the signal separation circuit, the vertical synchronization signal separation circuit, and the composite synchronization signal from the composite synchronization signal separation circuit. a PLL oscillation circuit that generates a reference signal for controlling the entire system, usually using the burst signal of each line from the bandpass filter as a reference, and the reference signal from the PLL oscillation circuit and the horizontal synchronization signal separation circuit. , a horizontal and vertical synchronization signal burst gate pulse that inputs the horizontal synchronization signal and vertical synchronization signal from the vertical synchronization signal separation circuit, respectively, and generates a reproduced horizontal synchronization signal, a reproduced vertical synchronization signal, and a burst gate pulse based on these signals. The reproduced vertical synchronizing signal from the horizontal/vertical synchronizing signal burst gate pulse regenerator and the vertical synchronizing signal from the vertical synchronizing signal separation circuit are input to the regenerator, and based on both signals, it is determined whether the input video signal is normal. and a detection means for determining whether or not the video signal is inputted, and when it is determined that a normal video signal is input based on the detection result by the detection means, a period in which there is no video signal within the vertical blanking period and a fixed signal are input. A gate circuit in the horizontal/vertical synchronizing signal burst gate pulse regenerator which gates only the burst signal of the next horizontal scanning line in the period extracts the burst gate pulse and reproduces the synchronizing signal from the burst gate pulse, When it is determined that a normal video signal is not being input based on the above detection result, a synchronization signal is regenerated from the burst gate pulse from the burst gate pulse generator that gates the burst signal of all periods of the input video signal. A synchronous signal reproducing circuit characterized in that it is configured to.