JPH03180946A - Address converter - Google Patents

Abstract

PURPOSE:To attain rapid processing by restricting a time delay from the updating of a logical address up to the generation of a physical address only by the delay time of a constant adder. CONSTITUTION:Since a latch circuit 9 is connected, a program counter 1 enters a logical address outputted from a logical address adder 3 at the timing preceding the timing of system clocks A, B, C.... Even if the logical address is outputted, the output data are latched by the latch circuit 9, so that a constant iTA is updated at the applying timing of the system clocks A, B, C.... Since the constant iTA can be added to the updated address signal and the physical addresses EAA, EAB... can be generated only after the delay of the added delay time t'0 of a constant adder 10 from the timing of the system clocks A, B, C..., the delay time of the adder 10 can be offset and rapid processing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address translation device used in a device that reads microprograms stored in a memory and executes various controls.

"Prior Art" FIG. 5 shows the storage status of programs stored in memory. In the example in the figure, from physical address 1000 to 1100
Store program No. l at the address, and change to physical address 2.
Program No. between address 000 and address 2100,
2 is stored.

In other words, a physical address refers to an absolute address for accessing memory.

On the other hand, address information within a program is written using logical addresses (also called relative addresses).

In the example in the figure, each word WRWR2 and
. . is stored in logical addresses 0 to lOO.

Generally, when developing a microcomputer program, it is often programmed using logical addresses rather than absolute addresses in consideration of the flexibility of development tools. The logical address is finally translated into a physical address by an address translation device, allowing access to the memory.

FIG. 3 shows a conventional example of an address translation device that translates a logical address into a physical address.

In the figure, 1 indicates a program counter. This program counter 1 stores the logical address at which the currently executed instruction is written.

That is, a constant generator 2 is provided for the program counter 1. The constant generator 2 and the program counter 1 are supplied with the same system clocks A, B, C, and C as shown in FIG.
... is given, and this system clock A, B, C...
・In synchronization with , the program counter 1 receives the addition result of the adder 3 and reads the next instruction from the logical address LA,
, LAC . . . and constants iTA, iT from the constant generator 2.

... is output, and the constants iTA, iTw... and the logical address output from the program counter 1 are added to the adder 3.
and returns the addition result to program counter 1. Program counter 1 transfers the addition output of adder 3 to the next logical address LA, , L at the next system clock A.
Ac and the next logical address L A
E, L A c... are output to the adder 3 again, and constants iTa, iTB... are output from the constant generator 2.
・Add and update the logical address.

In this way, the next logical addresses LA, LA, . . . are updated every time the system clocks A, B, C, . . . are supplied. Therefore, program counter 1 and constant generator 2
The section constituted by the adder 3 and the adder 3 will be referred to as a logical address generator 4.

Next logical address LA output from adder 3.

LA, . . . are manually input to the second adder 5. This adder 5 receives the base address BA from the base address generator 6.
is given, and the logical address 1. ABLAc...
The base address BA is added to the address AA to convert it into a physical address AA, which is then given to the memory 7.

``Problems to be Solved by the Invention'' According to the configuration shown in FIG. 3, as shown in FIG. . . , and the program counter 1 outputs the logical address LAA.

The constant iTA and the logical address LAA are added by the first adder 3 to obtain the next logical address LAI for reading the next instruction.
I and is input to the second adder 5.
The base address BA is added and converted to the physical address AA.

The first adder 3 and the second adder 5 have delay times t0 and tl.
is given. Therefore, the physical addresses AA, BB, ... given to the memory 7 correspond to the system clocks A, B.
, ...each t. +1. The signal is applied to the memory 7 at a timing delayed by .

In the memory 7, the contents of the accessed address are read out when an access time has elapsed from the time when the physical address signals AA, BB, . . . were applied.

The next instruction to be executed is determined from the read contents, and the subsequent address of the next instruction is calculated.

In this way, in order to start the operation of calculating the physical address from the time when the system clocks A, B, C, . . . are supplied, the first adder 3 and the second adder 5 have a delay time τ-t.

When ten t1 is given, there is a limit to the operating speed, which is an obstacle to increasing the speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address translation device that can offset the delay time of an adder and increase the speed.

"Means for Solving the Problem" In this invention, the clock given to the program counter is advanced in phase to the system clock, and the next logical address output from the logical address adder is taken in at a timing before the timing of the system clock. The fetched logical address is immediately given to the base address adder, and the base address adder adds the base address and the logical address stored in the program counter at a timing before the system clock generation timing.

This addition result can be used to latch an address obtained by adding this base address to a latch circuit at the timing of supplying the system clock. The second output of the latch circuit is input to a constant adder.

The constant addition calculator receives an address signal obtained by adding the constant output from the constant generator 2 and the base address provided from the latch circuit, and calculates a physical address by adding this constant and the address signal.

Therefore, according to the present invention, the addition of the logical address stored in the program counter and the base address is processed at a timing before the system clock timing, and when the system clock is supplied, a constant is added to the address that has already been added. do it.

Therefore, a physical address can be generated in a time corresponding to the delay time of one adder from the timing of the system clock, and high speed can be realized.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In Figure 1,
Portions corresponding to those in FIG. 3 are designated by the same reference numerals.

The feature of this invention is that the program counter 1 and constant generator 2 that constitute the logical address generator 4 give the logical address LA and constant iT, 1 to the logical address adder 3, and use them in the next tie-up. At the same time, the logical address LAA and constant iTA outputted from the program counter 1 and the constant generator 2 are directly taken out, and the logical addresses LA, LAI, . . . are added to a specially provided base address adder 8. A latch circuit 9 is provided to temporarily hold the addition result of the base address adder 8, and the latch output of the latch circuit 9 is used to generate a constant. The point is that the address translation device is constituted by a constant adder 10 that adds to the constant iTA output from the device 2.

In the configuration of this invention, the clocks given to the program counter 1 are system clock A, as shown in FIG.
It is possible to provide a clock CP whose phase is more advanced than that of B, C, . . . .

In other words, by providing the latch circuit 9, the program counter l receives the logical address output from the logical address adder 3 at a timing before the timing of the system clocks A, B, C, etc.
Even if the logical address is output, the output data is latched by the latch circuit 9, so that an address signal obtained by adding the base address to the logical address can already be obtained at the timing of supplying the system clock.

Therefore, by updating the constant iT6 at the timing when the system clocks A, B, C, . . . are applied, the constant iTA can be added to this updated address signal.

The addition delay time t' of the constant adder 10 from the timing of BC... physical address EA, with only a delay.

EA, . . . can be generated.

The operation of the present invention will be explained in more detail with reference to FIG.

FIG. 2A, B, C, . . . show system clocks.

These system clocks A, B, C... are constant generator 2
is given to update the constant iTA.

The clock CP has a phase that is t2 ahead of the timing of the system clocks A, B, C, .

Logical address LA stored in program counter 1
From the timing when a, LA++... are updated at the timing of the clock CP, the base address adder 8
Logical address LA^ after delay time t1.

The base address adder 8 outputs addresses CAA, CA, . . . which are obtained by adding the base address BA to LA, .

Therefore, for example, by providing the latch signal LCK to the latch circuit 9 with timing synchronized with the system clocks A, B, C, etc., addresses CA^, CAm, etc. can be latched by the timing of the latch signal LCK. can do. DAa in FIG.

DA, . . . indicate the latch outputs.

Address DA latched by latch circuit 9.

DAB... is given to the constant adder 10. The constants iTa, iTn, etc. are updated manually in the constant adder 10 at the timing of the system clocks A, B, etc., so the addition results EA, EA, ... are the same as each system clock A, Constant adder 10 from the timing of B,...
delay time t'. is applied to the memory 7 with a delay time of .

"Effects of the Invention" As explained above, according to the present invention, in an address conversion device that converts a logical address into a physical address, the time delay from the update of the logical address to the generation of the physical address is the delay time of the constant adder 10. can only be done.

Therefore, the time from the generation of a logical address to the generation of a physical address can be shortened, and the speed at which memory can be sequentially output can be increased, providing the advantage of enabling high-speed processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the invention in detail, 1 FIG. 3 is a block diagram for explaining the conventional technology, and FIG.
The figure is a waveform diagram for explaining the operation of the conventional technique, and FIG. 5 is a diagram for explaining the storage situation of the program written in the memory. 1: Program counter, 2: Constant generator, 3: Logical address adder, 4: Logical address generator, 6: Base address generator, 7: Memory, 8: Base address adder, 9: Latch circuit, 10: Constant adder.

Claims (1)

[Claims] (1) A. A logical address generator that generates a logical address to be generated at the next timing by adding the logical address stored in the program counter and the constant output from the constant generator using a logical address adder. , B. A base address adder that adds a base address to the logical address stored in the program counter; C. A latch circuit that latches the addition result of this base address adder; D. A latch output of this latch circuit. An address translation device comprising: a constant adder that adds a constant output from the constant generator and outputs a physical address for accessing a memory;