JPH03180956A - Information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing apparatus that executes data processing of each device while adjusting bus rights between a CPU and a direct memory access controller connected to a system bus. It is something.

[Conventional technology]

Conventionally, when performing DMA control in this type of device, the data and address buses are shared between the CPU and the DMA transfer hardware, so it is necessary to adjust the bus ownership. The transfer methods 1) and (2) are adopted.

(1) A method of transferring data using the time when the CPU is not accessing the bus (cycle cycle method).

(2) A method in which the DMA control circuit has priority and the CPU is stopped for transfer.

Of these, method (2) can be further subdivided into a method in which control is returned to the CPU for each byte of transferred data (byte mode), and a method in which control is returned to the CPU for each byte of transfer data (byte mode).
A! A method in which the IJ side retains the rights (continuous mode), and DM until the required number of bytes have been transferred.
It is divided into methods such as a method in which the A side has the rights (burst mode), etc.

[Problem to be solved by the invention]

Incidentally, this type of information processing apparatus is configured such that dual port memories are arranged in blocks so that data processing corresponding to a display via a serial baud can be processed independently of a random port.

When using dual port memory, connect it to a random port CPU and connect the CRT to the serial port.
It is often configured to connect a display.

However, when using scanners, printers, etc.
There is no choice but to use a random port, and if a situation occurs where the system operates simultaneously with the CPU, there is a serious problem that each process becomes extremely slow.

The present invention was made to solve the above problems, and by executing a predetermined pseudo write transfer cycle when data is read/write accessed by the serial port of a dual port memory, the presence or absence of a write transfer cycle is dual-controlled. An object of the present invention is to obtain an information processing device in which a port memory can be reliably identified.

[Means to solve the problem]

The information processing apparatus according to the present invention is provided with pseudo cycle execution means for executing a predetermined pseudo write transfer cycle on each image memory block prior to a data write cycle on each image memory block.

[Operation] In the present invention, when a data write cycle to each image memory block is requested, the pseudo cycle execution means executes a predetermined pseudo write transfer cycle to each image memory block prior to the data write cycle to each image memory block. This makes it possible to distinguish between read and write modes.

(Embodiment) FIG. 1 is a system block diagram illustrating the configuration of an information processing apparatus showing an embodiment of the present invention. Reference numeral 1 denotes a scanner that manually scans still images. 2 is a printer that outputs the print result. 3 is an SC5I controller that performs input/output between the scanner 1 and the printer 2; 4 is a high-definition CRT display, 5 is an interface, and 6 is a pointing device for specifying coordinate information, icons, etc. by specifying 2 keys. 7 is the interface (1/F),
Processes coordinate information etc. from the pointing device 6. 8 is memory (static RAM), sub CPU 9
Stores program data. A serial interface 10 inputs and outputs data on the serial port side of a dual port memory (dual photo RAM) 11, and has a built-in timer for periodically referencing the state of the pointing device 6. 11 is a dual port memory for a scanner and printer having a random port and a serial port; 12 is a dual port memory for the CRT display 4; 13 is a memory controller (DMA
In C), refreshing of the dual photomemories 11 and 12, serial reading, serial writing, pseudo write transfer timing, CPU access, and two-dimensional DMA are performed.

14 is an arbiter (illil stopper), sub CPU9,
Main CPU33. DMA controller (DMAC) 1
In addition to controlling the adjustment of the bus right of sub-CPU 9.
Interrupt hunt shake of the main CPU 33 is performed. 15
is an image compression/decompression device that compresses and decompresses image data. Reference numeral 16 denotes a bus width adjustment device that adjusts the compression code of the image compression/decompression device 15 to the bus width of the bus 44 and outputs data. A device 17 performs XY conversion on the image data. A device 18 processes thinning and interpolation of image data. Buffers 19 to 21 drive the bus.

22 is FROM, which stores a boot program and interrupt vectors when the power is turned on. 23 is a static RAM used at startup, and 24 is a device that manages time and stores system management information even when the power is turned off. 2
5 is a counter for switching processes and measuring time.

26 is an interrupt controller that outputs a vector when an interrupt occurs. 27 is an interface that supports serial communication. 28 is a modem connected to a public line, and 29 is an interface for inputting keys from a keyboard 30. 31 is Dynaku Tsuku RA
M (DRAM) stores program data on the system side. A memory controller (DMA controller) 32 controls refresh of the DRAM 31 and DMA between the memory and each device. 33 is a main CPU, and 34 is a device which performs address decoding, interrupt control, and control of each control line. 35
36 is a port that has built-in fonts of various typefaces and dictionaries for kana-kanji conversion, etc., and 36 is an interface that supports IEEE802.
3 108ASE5 (so-called ETHRNET) is supported. Reference numeral 37 denotes a device constituting the bus width adjusting means according to the present invention, which interfaces the 8-bit input/output 5CSR interface 3B (constituting a direct memory access device) with the data bus 45 having a 32-bit data width. 39 is a hard disk with 5CSII/F, 40 is a bus width adjustment device, and 41 is an interface device that interfaces between the floppy disk controller and the bus 45. 42 is a 3.5-inch floppy disk drive, 43 is a bus with a data width of 16 bits, 44.45 is a bus with a pig width of 32 bits, 46 is a bus with a data width of 16 bits, and 47 is a bus with a data width of 16 bits. 1 that can be accessed only from CPU9
This bus has a data width of 6 bits, and is configured so that the polarity of the most significant bit of this address line can be inverted with respect to the polarity of the address line coming out from the sub CPU 9.

In the information processing device configured as described above, when a data write cycle for each image memory block (in this embodiment, the dual port memory 11, etc.) is requested from the 5C3I controller 3, etc., the pseudo cycle execution means (in this embodiment, the The memory controller 13) performs a predetermined pseudo write transfer cycle (details will be described later) to each image memory block prior to a pig write cycle to each image memory block of the dual port memory 11.
The read/write mode can be identified.

FIG. 2 is a circuit block diagram showing an example of polarity inversion processing of the most significant bit of the address line of the sub CPU 9 shown in FIG. Based on exclusive OR circuit (
The Q output is sent to EX-OR circuit) 101.

FIGS. 3(a) to 3(h) show the arbiter 14 shown in FIG.
FIG. 1 is a detailed block diagram illustrating the configuration of FIG.

In these figures, 201 to 205 are EXOR circuits,
206 is an inverter, 207 to 211 are EX-OR circuits, 212 is an inverter, 213 and 214 are NAN'D circuits, 215 is an inverter, 216 is an AND circuit, 217 is a NAND circuit, 218 is an AND circuit, 219 is a NAND
Circuit, 220 is an AND circuit, 221 to 223 are JK Philip flops (JKFF) with reset terminal, 224
is a NOR circuit, 225 is an inverter, and 226.227 is an NOR circuit.
OR circuit, 228 is an inverter, 229 to 232 are NO
R circuit, 233 is an OR circuit, 234 and 235 are D flip-flops (DFF), 236 and 237 are inverters,
238 is NOR circuit, 239 is DFF, 240 is JKF
F, 241 is an inverter, 242 is a NAND circuit, 24
3 is an AND circuit, 244 is an inverter, 245 to 247
is OFF, 24B is NAND circuit, 249 is AND circuit, 250 is JKFF, 251.252 is DFF, 253
is an AND circuit, 254 is an inverter, and 255 to 257 are DFFs.

258 is a NAND circuit, 259 is an AND circuit, 260 is a JKFF, and 261.262 is a DFF.

263.264 is a DFF, 265 to 267 are NAND circuits, 268 is an inverter, 269.270 is a NAND circuit, 271 is an inverter, 272273 is a NAND circuit, 274 is an inverter, 275.276 is a DFF, 27
7 to 279 are NAN0 circuits, 280 is an inverter, 28
4.282 is an AND circuit, 283 is a NOR circuit, 284
is a 3-state buffer, 285 is an inverter, 286 is a NOR circuit, 286 is a NOR circuit, 287 is an inverter, 288 is a NOR circuit, 289 is an inverter, 290.2
91 is a NOR circuit, 292 is a 3-state buffer, 29
3 is an inverter, 294 is a NOR circuit, 295 is an inverter, and 296 is an N.

R circuit, 297 is an inverter, 298 is a NOR circuit, 2
99 is an inverter, 300 is a NOR circuit, 301 is an inverter, 302 is a NOR circuit, 303 is a NOR circuit, 3
04 is a 3-state buffer, 305.306 is an inverter, 3.07-310 is a NOR circuit, 311 is an AND circuit, 312.313 is a NOR circuit, 314 is a 3-state buffer, 315-326 is an OR circuit, and 327 is a AND
328 is a 5RFF, 329 is a NANDAND circuit 0 is an OR circuit, 331 is a NANDAND circuit 2 is an OR circuit, 333 and 334 are NAND circuits, 5.336 is an AND circuit, and 337.338 is a 5RFF.

FIG. 4 is a block diagram illustrating the peripheral circuit configuration of the arbiter 14 shown in FIG. It is a path transceiver.

Next, the start-up processing operation of the sub CPU 9 etc. shown in FIG. 1 will be described with reference to FIGS. 5 and 6.

FIGS. 5 and 6 are flowcharts illustrating an example of a procedure for starting up the sub CPU 9 shown in FIG. 1.

Note that (1) to (9) and (11) to (25) indicate each step.

When the power is turned on, the main CPO 33 first starts up, inputs the values of the stack pointer and program counter at the time of reset from the FROM 22, and performs startup processing.

At this time, the sub CPU 9 displays a cursor on the dual port RAM 11 based on the signal from the bonding device 6, controls the 5CS1 controller 3, and controls the scanner 1. Step (1)
), check the size that includes the entire program,
Set the number of words to transfer. Next, the transfer start address as seen from the main CPU 33 of the dual port memory 12 is set (2).

Next, data including programs and the like is transferred from the FROM 22 or DRAM 31 to the dual port memory 12 (3). Next, a data sum is performed to add the data value to a certain register or memory (4), and it is determined whether the transfer is completed, that is, whether the number of transfers remains is "0" (5), and N.

If so, return to step (3), and if YES, transfer the added data value (checksum) (6).

Next, the JSTART signal is given to the arbiter 14, and the sub CPU 9 to which the reset signal has been applied until now starts (7).

Next, the sub CPU 9 inputs the stack pointer and program counter from the dual port memory 12, and statically reads the program loaded in the dual port memory 12 according to the flow shown in FIG.
Load it into AM8 and invert the most significant bit of the address so that the interrupt vector of sub CPU9 is switched to static RAM (SRAM>8).

Next, wait for the ACK interrupt to occur (8), and when the interrupt occurs, write the interrupt response command J I QACK to the IBM register (9), and end the process.
The process moves on to processing by the sub CPU 9.

The size including the entire program is checked and the number of words to be transferred is set (11). Next, dual photo memory 12
The transfer start address as seen from the main CPU 33 is set (12).

Next, data including programs and the like is transferred from the FROM 22 or DRAM 31 to the dual port memory 12 (13). Next, a data sum is performed to add the data value to a certain register or memory (10), and it is determined whether the transfer is completed, that is, whether the number of transfers is "0" or not (15), and N.

If so, return to step (13), if YES, determine whether the checksum is OK] 6), if no, proceed to step (23) or later; if YES, write data to the inversion register (17), and write the data to the SRAM8. To determine whether the checksum is OK [1], N.

If so, proceed to step (23) or later, if YES, VR
Write normal status to AM buffer (19), 1
Write interrupt command KIQACK to 8M register (20). Wait for the ACK interrupt to occur21)
When an interrupt occurs, an interrupt clear command KIQCLR is written to the 18M register (22), and the process ends.

On the other hand, if NO in steps (16) and (18), write the error status to the VRAM buffer (2)
3), Write the interrupt command KIQACK to the 18M register (24). It waits for an ACK interrupt to occur (25), and when the interrupt occurs, it writes an interrupt clear command KIQCLR to the 18M register (26) and ends the process.

Specifically, the most significant bit of the address is input to one side of the EX-OR circuit 1゜1 shown in FIG. 2, and the output of the flip-flop 102 is input to the other side.
By inverting the output of 2, the polarity of the most significant bit of the address is switched. Next, a message indicating that the program transfer has been completed is written to the communication buffer with the main CPU 33 provided in the dual port memory 12, and
The KrAcK signal is given to the arbiter 14, and the main CPU 3
This is done by applying an interrupt signal to 3. Main CPIJ3
3 receives the interrupt signal from the arbiter 14 and JIACKs
is sent to the arbiter 14 and interrupts the sub CPU 9.

The sub CPU 9 sends the KIQCLR signal to the arbiter 14 as an interrupt clear signal, and the initial operation of the sub CPU 9 ends.

Next, by transferring the bitmap data to the dual port memory 12, the bitmap image can be displayed on the CRT display 4 through the interface 5.

Next, the O8 (operating system) and application program (AP) are transferred from the hard disk 39 to the dynamic RAM 31, but in this system, the DMA controller (DMAC) 32 and bus width adjustment device 37 are normally connected to the main CPU 33 and the SC3I controller 38. 8-hit width data transfer is being performed between
When outputted from the I controller 38 and inputted manually to the bus width adjustment device 37, the bus width adjustment device 37
When entering the MA transfer mode and writing data in the dynamic RAM 3+ to the hard disk 39, the bus width adjustment device 37 outputs a DMA request to the DMA controller 32.

The DMA controller 32 requests bus ownership from the main CPU 33, and when the main CPU 33 releases the bus,
The DMA controller 32 takes control of the bus and writes 32-bit width data to the bus width adjustment device 37. The bus width adjustment device 37 cancels the DMA request, thereby also releasing the DMA controller 32 and the main cPU 33 taking control of the bus again.

On the other hand, the bus width adjustment device 37 decomposes 32-bit width data into 8-bit width data and writes the data to the SCSI controller 38 when a request is being output. When the four writes are completed, there is no data in the bus width adjustment device 37, so the bus width adjustment device 37 outputs a DMA request to the DMA controller 32 again and repeats the above operation. 5cs
The r controller 38 transfers data to the pigeon disk 39 in accordance with the SC3I standard. A series of operations are performed until data of a fixed block length is transferred. The bus width adjustment device 37 is connected to the D
MA transfer end signal.

When a transfer end signal is generated from the NE or SCS I controller 38, the DMA transfer mode is automatically terminated.
In normal mode, SC3I controller 38 and main C
The PU 33 can now communicate. Also,
Data on hard disk 39 is transferred to Dyna Ritsuta RAM 3+
When writing to C, SC5I to the lotus width adjustment device 37.
The only difference is that the bus width adjustment device 37 outputs a DMA request to the DMA controller 32 after writing the data in the controller 38 four times, and that the data transfer direction is reversed.The other operations are to write to the disk. The operation will be the same.

In this way, by providing the bus width adjustment device 37, even if there is a device in progress of DMA transfer, the main CPU 3
3 can execute a program by taking control of the bus between transfers without having the DMA controller 32 take control of the bus all the time.

However, the DMA10 device, in this example 5C
In the SI controller 38, a problem occurs when the read signal and the write signal are processed by a simple OR operation from the CPU and the bus width adjustment device 37. The read signal and write signal output from the bus width adjustment device 37 are D
Although they only occur during MA, the read and write signals output from the CPLI are transmitted to the CPU even during DMA.
is output for other Ilo when it has the bus right. Naturally, this timing is different from the read signal and write signal generated from the lotus width adjustment device 37, so there is a possibility that the SCSR controller 38 will malfunction. To prevent this, provide a signal indicating that DMA is in progress,
The method of switching the signal between the bus width adjustment device 37 and the CPU, and the method of switching the signals between the bus width adjustment device 37 and the CPU, and the method that allows the CPU to access the SCSI controller only when the CPU is accessing the SCSI controller (during chip selection).
Although there is a method of inputting read/write signals from the memory, the latter method is optimal in order to satisfy the timing.

FIG. 7 is a block diagram illustrating the connection relationship between the bus width adjustment device and the DMA110 device, where 401 is the bus width adjustment device, 402 is the DMA110 device, and 40
3,404 is an OR gate, and 405,406 is an AND gate.

DMA10 device 402 and bus width adjustment device 40
1 DMA transfer is performed using a REQ signal and an ACK signal. Normal CPU access', machitube select signal, read signal, write signal y, < DMA I10 device 402. Both bus width adjustment devices 401 are manually operated, and reading and writing to the DMA110 device 402 is accessed in 8 bits. When a DMA command is issued and a REQ signal is output from the DMA110 device 402, the bus width adjustment device 401 enters the DMA transfer mode and transfers data to and from the system bus in 32 bits. When the bus width adjustment device 401 receives the REQ signal, it returns an ACK signal, but at the same time, depending on the transfer direction, the bus width adjustment device 401
A by setting the RD signal or DMAWR signal to LOW level.
The RDB signal and WRB signal are sent to the DMA110 device 402 via the ND gate 405406. CPU is DM
If the system bus is not occupied by AC, each I1
A read signal and a write signal may be issued for 0,
Simply AND gate the read signal and write signal 405, 4.
If this is ORed with 01 and input to the RDB signal and WRB signal of the DMA110 device 402, the DMA transfer may not be performed normally.

Therefore, the chip select signal, read signal, and write signal are ANDLed by OR gates 403 and 404, and then
If the gates 405 and 406 are ORed, no malfunction will occur. Of course, each of these gates can also be built into the bus width adjustment device 37.

Also, the bus width adjustment device 40. The operations of the floppy disk controller 41 and 3.5 inch floppy disk drive are substantially similar.

The DMA controller 32 has three sets of DMA channels, and parallel transfer between a hard disk and a floppy disk is also possible. Further, the operation of the arbiter 14, which controls the access of the main CPU 33 and the sub CPU 9 to the dual port memory 11.12 at the same time, will be explained with reference to FIG. 3(a).

EX-OR circuits 201 to 205 are used for address selection of the dual port memory 11.12 when viewed from the sub CPU 9, and EX-OR circuits 207 to 211 are used for main cp
Dual port memory 11.12 when viewed from u33
used for address selection. Unnecessary gates are connected so that the output is HIGH.

Ports KLVL1 to 5 of EX-OR circuits 201 to 205
and ports JLVL of EX-OR circuits 207 to 211
For I~5, enter the polarity level opposite to that of the address to be selected, and for ports KAA1~5 and JAA1~
A bit is connected to 5 to determine the address to be selected. As a result, when the sub CPU 9 outputs the address of the dual port memory 11.12, the EX
-The outputs of the OR circuits 201 to 205 all become HIGH, and the address strobe signal KASB becomes LOW, so the output of the inverter 206 becomes HIGH.
The output of the NAND circuit 213 becomes LOW. the result,
The output of the NOR circuit 217 becomes HIGH, and at the rising edge of the CLK signal, the Q output of the JKFF 222 becomes HIGH and the inverted Q output becomes LOW. The NOR circuit 217 also selects the memory controller 13 with a signal K L CS B
Even if h<L 0W, the output becomes HIGH. Similarly, from the main CPU 33 to the dual port memory 1112
When the address is output, EX-OR circuits 207 to 2
Since all the outputs of inverter 11 become HIGH and the address strobe signal JASB becomes LOW, inverter 2
The output of NAND circuit 219 becomes HIGH, and the output of NAND circuit 219 becomes LOW. As a result, the output of the NAND circuit 219 becomes HIGH, and at the rising edge of the CLK signal, the JKF
The Q output of F223 becomes HIGH, and the inverted Q output becomes LOW. The NAND circuit 219 also outputs HIGH even when the signal JLCSB for selecting the memory controller 13 becomes LOW.

Furthermore, when the memory controller 13 sets the LBRB signal to LOW to perform DMA transfer, the inverter 21
5 becomes HIGH, and JKF at the rising edge of the CLK signal.
The Q output of F221 becomes HIGH1 and the inverted Q output becomes LOW. In this way, when the inverted Q outputs S3 and 56311 of JKFF221 to 223 become LOW at the same time, N
The output S8 and the output ■ of the OR4 circuits 227 and 232 become HIGH, and as a result, the output ■ of the NOR circuit 224 becomes LOW and NO.
The output (2) of the R circuit 229 becomes LOW.

In other words, only the output ■ becomes HIGH, and the output ■ becomes HIGH.

Output @ becomes LOW. Similarly, output S3. S6 is LO
W, if the output is Sll or HIGH, only the output ■ is H
The output becomes IGH, and the output ■ and the output ■ become LOW.

Similarly, output S3. Sll is LOW, output S6 is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW.

Similarly, output S6. Sll is LOW, output S3 is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW. Also, when -output S3 is LOW alone, when output S6 is LOW alone, only output ■ is LOW.
W, and when the output S11 is LOW alone, only the output ■ becomes LOW.

In other words, the arbiter 14 has a fixed priority order,
The output is defined as Sll>S6>33. In this way, when either of the outputs ■3■ and ■ becomes HIGH, the output S14 of the OR circuit 233 also becomes HIGH, and when the CLK signal falls, the inverter 236 outputs
FF234 latches output S14 and output S becomes Q output
15 becomes HIGH. The inverted Q output becomes LOW, and since this is connected to the inverted S output of DFF235,
S16, which is the inverted Q output of DFF235, immediately goes LOW.
becomes. As a result, the output S7 of the NOR circuit 226 becomes the same level as the output ■, and if the output ■ is HIGH, the output S7 is also HIGH, and the output S6 is LOW.
The output S8 of the NOR circuit 227 will not become TIGH even if That is, when the output ■ becomes HIGH and the inverted Q output S16 of the DFF 235 becomes LOW, the NOR circuit 224 does not cause the output ■ to become LOW even if the output S6 becomes LOW. This allows stable access. Similarly, the output S13 of the NOR circuit 231 becomes HIGH due to the NOR circuit 230 when either the output ■ or the output ■ is HIGH, and even if the output S11 becomes LOW, the output ■ of the NOR circuit 232 becomes HIGH.
Hll: It will not happen. That is, when the outputs ■ and output ■ become HIGH and the output S16, which is the inverted Q output of the DFF 235, becomes LOW, even if the output Sll becomes LOW, the NOR circuits 224 and 229 cause the outputs ■ and output ■ to become LOW.
There is no way to set it to LOW. In this way, once a lower priority run cycle is started, it cannot be interrupted by higher priority inputs until the run cycle is finished. Output Sit which becomes the inverted Q output of JKFF223
is LOW and the output 2 becomes HIGH, and the output S16, which is the inverted Q output of the DFF 235, becomes LOW. When the execution cycle begins, the LJB output also becomes LOW by the inverter 254 in FIG. 3(b). The LJB output is connected to the tri-state input of the address buffer 352 and the tri-state input of the data buffer 353 of the main CPU 33, so that the main CPU 33 has bus ownership of the bus 43. The memory controller 13 accesses the dual port memory 11.12 according to the address and returns data acknowledge signals LDTK, B to the arbiter 14. In the arbiter 14, the inverter 271. shown in FIG. 3(c). It is output as a JDTAK signal through a NAND circuit 269270. This signal is returned to the main CPU 33, and the main CPU 33 sets the JASB signal to HIGH, thereby completing the cycle. This allows the third
The output SIO of the AND circuit 220 in figure (a) becomes HIGH, the output S17 of the NOR circuit 23 becomes LOW,
Q output S15 of DFF234 is LOW, inverted Q is HIGH
It becomes H.

Here, when the CLK signal goes from LOW to HIGH, J
Output S11, which is the inverted Q output of KFF223, is HIGH!
(Then, the output ■ of the NOR circuit 232 is LOW, and the output LJAS of the AND circuit 259 shown in FIG. 3(b) is also LOW.
As a result, bus ownership of the image bus is released from the main CPU 33. At the rising edge of the CLK signal, JKFF22
At the same time as 3 and 8, output 316, which becomes the inverted Q output of DFF 235, also goes high.
H, and the output S3. S6. Sl 1 (7) Enter adjustment cycle for each signal.

Here, output S6 only or output S3. If S6 is LOW, the sub CPU 9 takes control of the bus as described above, and the data acknowledge signal LDTKB of the memory controller 13 is activated.
similarly ends the bus cycle.

On the other hand, in the arbiter 14, there is a DFF 251 shown in FIG. 3(b).
．． 252.261.262, and if the main CPU 33 and sub CPU 9 access is close, LA
In order to prevent the SB signal and LDTKB signal from affecting the memory controller 13 and each cPU9.33 due to delay time, etc., the LJA signal is
The S signal and LKAS signal are separated so that they do not come close to each other. Even if the output ■ becomes LOW and immediately the output ■ becomes HIGH, the Q output of the DFF 261 becomes LOW, the inverted Q output of the DFF 262 starts to become HIGH, and the LKAS signal becomes HIGH. The same applies to the LJAS signal. Note that the LASB signal, LUDSB signal, LLDSB signal, LRW signal, L
Each signal of the CSB signal and the JDTA shown in Figure 3(C)
The K signal, KDTAK signal, JBER signal, and KBER signal all become valid unless either the LJAS signal or the LKAS signal becomes HIGH. Thereby, independent access between the main CPU 33 and sub CPU 9 can be performed at high speed, and access between the main CPU 33 and the sub CPU 9 can be performed safely.

By the way, the JKFF221 is activated by the bus request signal LBRB from the DMA controller 13 on the image bus.
When the output S3, which is the inverted Q output of
TAK signal, KDTAK signal, JBER (g, KBE
All of the R signals are not valid unless either the LJAS signal or the LKAS signal is HIGH.

Thereby, individual access between the main CPU 33 and sub CPU 9 can be performed at high speed, or close access can be performed safely.

By the way, the JKFF 22
Output S3 becomes the inverted Q output of + or becomes OW and output ■
When is HIGH, as shown in Figure 3(b),
The inverted Q output of the DFF 239 becomes HIGH at the rising edge of the CLK signal, and the LB becomes the output of the NAND circuit 242.
GB signal becomes LOW. This indicates that the bus right has been transferred to the DMA controller 13, and the DMA controller 13 sets the LBGAKB signal to LOW and the LBRB signal to HIGH. As a result, the output of the inverter 241 becomes HIGH, and the Q output of JKFF240 becomes LOW.
becomes. As a result, the LBGB signal becomes HIGH.

The DMA controller 13 starts data transfer and holds the LBGAK signal LOW until the data transfer is completed. When the data transfer is completed and the LBGAK signal is set to HIGH, the output S of the AND circuit 216 shown in FIG.
2 becomes HIGH, the output S17 of the NOR circuit 238 becomes LOW, and the output S15 becomes the Q output of the DFF 234.
is set to LOW.

At the rising edge of the CLK signal, output S3, which is the inverted O output of JKFF221, becomes HIGH, and at the same time, 0FF235
The output S16, which is the inverted Q output, also becomes HIGH, and the output (2) becomes LOW, entering the abitration cycle again. Access to the main CPU 33 is indicated by the JASB signal being LOW in a normal cycle, but in order to synchronize the software of the main CPU 33 and sub CPU 9, a read and write cycle that must not be divided, a so-called read-modify-write cycle, is performed. be.

At that time, the JRMCB signal from the main CPU 33 is LOW.
By becoming aware of this cycle.

This JRMCB signal is input to the AND gate shown in Fig. 3(a), and the JAS B signal becomes HIGH. In a normal cycle, output 10 becomes HIGH and the cycle ends, but when the JRMCB signal becomes LOW In this case, the read-modify-write cycle is supported by not terminating the cycle. On the other hand, sub-cp
The u9 side does not have a KKRMCB signal and supports the following processing.

The KRW signal is HIGH1, that is, the read cycle is KA.
The SB signal becomes LOW, then the KUDSB signal or KLDSB signal becomes LOW, the dual port memory 11 or the dual port memory 12 is read, and the memory controller 13 sets the L DTA K B signal to LOW.
OW, and the arbiter 14 outputs the KDTAK signal. This allows the KUDSB signal or KLD
The SB signal becomes HIGH, the KASB signal remains LOW, the KRW signal becomes LOW, and the KUDSB signal or KLDSB becomes HIGH again to write to the dual photo memory 11 or dual port memory 12. The memory controller 13 turns the LDTAKB signal LOW again.
shall be. As a result, the KU including the KASB signal is now
The DSB signal or KLDSB signal goes HIGH and the cycle ends.

On the other hand, the memory controller 13 uses LAS for all cycles.
This is a period in which the B signal is LOW, and the memory controller 13 itself does not support a to-modify write cycle. For this reason, DFF245-247. JKFF
250. LDTAKB once by NAND circuit 24B
The signal goes LOW, and the KRW signal goes from HIGH to LOW.
When switching to , the LKAS signal is set to LOW once, that is, the LASB signal is set to HIGH once.

When the LDTAKB signal becomes LOW, the inverter output LDT of the inverter 271 shown in FIG. 3(c) becomes HIGH.
becomes H, and the Q output of JKFF250 becomes HIGH.

When KRW goes from HIGH to LOW, DFF246,
Since the Q output of DFF247 is HIGH and the inverted Q output of DFF245 is HIGH, the rise of the CLK signal is 2.
During this period, the LKAS signal is LOW and the LASB signal is HIGH.
It becomes H. The arbiter 14 thus supports read-modify-write cycles of 2f class, and does not change the rights to the image bus during this time. Also,
The LASB signal always goes LOW twice.

The arbiter 14 also supports interrupt handshaking between the main CPU 33 and sub CPU 9, and
3, when the signal JD1 shown in FIG. 3(g) is set to LOW and the signals JRW and JCSB are set to LOW, the 0FF263.264 and the NAND circuit 265 shown in FIG. Between, J
The JB signal becomes LOW, and the OR circuit 32 in FIG. 3(g)
4.315 causes the J I QACK signal to go LOW. As a result, the output of the OR circuit 330 becomes LOW, and N
The output of the AND circuit 331 becomes )(IGH, and NA
The KINTB signal output from the ND circuit 329 becomes LOW, and this signal becomes an interrupt signal to the sub CPU 9.

The sub CPU 9 LOs the KDI signal shown in FIG. 3(g).
When KRW signal and KCSB signal are LOW as W,
DFF275.276 and NAND shown in Figure 3(C)
The circuit 279 causes the KKB signal to be LOW from one rising edge of the CLK signal to the next rising edge, as shown in FIG. 3(h).
The OR circuits 326 and 322 turn the K I QACK signal LOW. As a result, the output of the OR circuit 332 becomes LOW, the output of the NAND circuit 333 becomes HIGH, and the JINTB signal, which is the output of the NAND circuit 334, becomes LOW.
It becomes an interrupt signal to U33, and at the same time the NAND circuit 32
The KINTB signal, which is the output of 9, is returned to HIGH and the interrupt signal is cleared. Do not interrupt the other party's CPU,
To clear only your own interrupt signal, use the main CPU
33 makes the JD2 signal LOW instead of the JDI signal, and the sub CPU 9 makes the KD2 signal LOW instead of the KDI signal, the JIQCLR signal and KIQCLR signal become LOW.
and clears the interrupt. Also, the signal JD3. With signal KD3 LOW, J
RW signal, JC3B signal LOW, KPW signal, KC3
When the B signal is LOW, the JMSKS5 T signal and KMSKST signal are LOW, and the 5RFF3
The Q outputs of 28 and 337 become HIGH, and the OR circuit 33
The output of 0,332 will no longer go LOW, and no interrupt signal will be generated. JD4 signal, KD4 signal L
As OW, set the JRW signal and JCSB signal to LOW,
The interrupt can also be canceled by setting the KRW signal and KCC3B signal to LOW. Also, if the JD5 signal, JRW signal, and JC3B signal are set to LOW from the main CPU 33, the KRESB signal can be set to HIGH, and if this is used as a reset signal for the sub CPU 9, the main CPU
The sub CPU 9 can be started from 33. J.D.
6 signal, JRW (i number), and JC3B signal are set to LOW (see FIG. 8), the sub CPU 9 can be reset again.

The data transfer process will be specifically explained below, taking as an example a case where a window and a cursor are displayed on the CRT display 4 using the dual port memory 12.

Not all areas of the dual port memory 12 are used for display 6, and some areas are completely free for RA.
It can be used as M. This dual port memory 12 can be accessed from both the main CPU 33 and the sub CPU 9, and is therefore ideal as a communication buffer. An arbiter 14 is used to interrupt the other party, and the state of the command or response at that time is exchanged in the communication buffer in the free area of the dual port memory 12.

In this system, the sub CPU 9 displays the cursor, and the main CPU 33 creates windows and rewrites the contents of the windows. Therefore, main C
When the PU 33 uses the VRAM, it writes a window rewriting request command and window coordinates in the communication buffer, issues a J I QACK signal command to the arbiter 14, and interrupts the sub CPU 9. The sub CPU 9 receives the window rewrite request command from the communication buffer using the KINTB signal, which is an interrupt signal, and turns on the busy flag. Next, the coordinates of the four corners of the window are taken, and a clipping operation is performed on the window where the cursor is displayed. As a result, if the cursor and the main CPI 333 overlap with the window to be rewritten, the sub CPU 9 erases the cursor and restores the original image to that area. Then, KIQAC for arbiter 14
A K signal is issued to cause the main CPU 33 to generate a JINTB signal as an interrupt signal. The main CPU 33 rewrites the window in response to the interruption in response to the window rewrite command. If the cursor and window do not overlap, the KIQACK signal is issued without erasing the cursor. When the main CPU 33 finishes window rewriting, it writes an end rewriting command in the communication buffer and sends a JIQACK signal to the arbiter 14.
A QACK signal is issued to cause the sub CPU 9 to generate a KINTB signal as an interrupt signal.

Sub CPtJ9 thereby sets the busy flag to 0FF.
The main CPU issues a KIQACK signal to the L/arbiter 14, and receives the generated JINTB signal interrupt as a response to the termination command. Sub CPU9
In addition to handling interrupts, the cursor is displayed in a separate routine, and the coordinate values of the pointing device are read every time a timer interrupt occurs in the interface 10, and if there is a difference from the previous one, the coordinate values are saved and used for the next one. Check the busy flag that turns ONeOFF in the interrupt routine, and if it is ON, clip the rewrite window with the cursor window, if there is an overlap, do not display the cursor, and if there is no overlap or the busy flag is OFF, display the cursor. Cursor display is to save the image in the cursor window, display a cursor such as an arrow, and when moving the cursor to another location, return the saved image and save the image again at the moved position. .

Next, the cursor/window processing operation in the information processing apparatus according to the present invention will be explained with reference to FIGS. 9(a) to 9(e).

FIGS. 9(a) to 9(e) are flowcharts illustrating an example of a cursor/window processing procedure in the information processing apparatus according to the present invention. In addition, (1) to (9), (
11) to (19) and (21) to (26) indicate each step. Hereinafter, the process will be explained sequentially starting from the process shown in FIG.

When the timer interrupt processing occurs, the sub CPU 9 (1)
Read the coordinate values from the pointing device 6 (2
), determine whether there is a difference from the previous coordinate values 3)
, if NO, return to step (1); if YES, save the current coordinate values (4).

Next, determine whether the busy flag is ON or not 5).
If NO, the process proceeds to step (9) and subsequent steps; if YES, the receiver obtains the coordinates of the four corners of the rewrite window (6). Then,
Try clipping in the cursor window 7), judge whether there is overlap 8), and if YES step (1)
> If the answer is No, display the cursor (9) and return to step (1).

On the other hand, the communication interrupt process determines whether a window rewrite request has occurred, as shown in FIG.
2) Receive the coordinates of the four corners of the rewrite window (13)
. Next, try clipping in the cursor window 14)
, it is determined whether or not there is an overlap (15), and if No, the process proceeds to step (17) and subsequent steps; if YES, the cursor is deleted (16), a response command is issued (17), and the process ends.

On the other hand, if the determination in step (11) is No, the busy flag is turned off (18), a response command is issued (19), and the process is terminated.

On the other hand, the main CPU 33 sends the coordinates of 4@ of the rewrite window to the communication buffer (21
), issue a window rewrite request command 22), wait for a command response from the sub CPU 9, etc. 23), and when a response is received, rewrite the window (2
4) Issue a command to end window rewriting (
25). Next, the process waits for a command response from the sub CPU 9 or the like (26), and ends the process.

Next, while referring to FIGS. 10(a) and (b), the sub-CP
The dragging IA process performed by U9 and the main CPU 33 will be explained.

FIGS. 10(a) and 10(b) are flowcharts illustrating an example of a dragging process procedure performed by the sub CPU 9 and the main CPU 33 in the information processing apparatus according to the present invention.

Note that (1) to (18) and (21) to (29) indicate each step.

The sub CPU 9 sends the cursor position to the communication buffer (
1) Issue an interrupt indicating that the left key is ON 2) Wait for a command response (3).

Next, determine whether it is a dragging command or not 4), N
If o, perform another process, if YES, take the window frame size position (5) and turn off the arrow cursor (6)
, the window frame is displayed in reverse (7). Next, wait for a timer interrupt to occur (8), and when the interrupt occurs, read the coordinate values of the pointing device 6 (9),
To judge whether there is a difference from the previous coordinate value 10), N
If YES, the process returns to step (8), and if YES, the coordinate values are saved (11) and the window frame position is changed (I2). Next, display the window frame 13), determine whether the key is in the OFF state 14), if NO, return to step (8); 3) If YES, transfer the window frame size position 15),
It issues an interrupt indicating that the left key is OFF (16) and waits for a command response to occur (17). Next, a command response is issued (18), and the process ends.

On the other hand, as shown in FIG. 10(b), the main CPU 33
When an interrupt is issued in step (2) above, the window at the cursor position is checked (21), it is determined whether it is a dragging area or not (22), the window frame size, position, etc. are sent to the communication buffer (23), and a dragging command is issued. (24). Next, it is determined whether there is a command response (25), and if YES, the window frame size and position are taken (26).

Next, the window is rewritten (27) and a window rewriting end command is issued (28). Next, it waits for a command response (29), and when the command response is issued, the process ends.

Next, the pop-up menu display processing operation of the information processing apparatus according to the present invention will be explained with reference to FIGS. 11(a) and 11(b).

FIGS. 11(a) and 11(b) are flowcharts illustrating an example of a pop-up menu display processing procedure performed by the information processing apparatus according to the present invention.

Note that (1) to (29) and (31) to (48) indicate each step.

First, the sub CPU 9 sends the cursor position to the communication buffer (1) and issues an interrupt indicating that the right key is ON (2).
. Then, wait for a command response 3),
If YES, it is determined whether it is a pop-up menu command (1), if YES, the pop-up window row is read out (5), and the arrow cursor is turned off (6). Next, issue a response command 7) and wait for a command response 8). If YES, move the arrow cursor to o.
N (9), please judge whether the right key is OFF or not (10)
, if YES, proceed to step (24) and later, turn off the arrow cursor, and judge whether it is the selection area or not.25
), if YES, press the right key to 0FFL/ and issue an execution interrupt (26). Next, wait for a command response (28), and if YES, turn the arrow cursor ONL.

(29), the process ends.

On the other hand, if the judgment in step (25) is No, turn off the right key and issue a non-execution interrupt.
Proceed to 8).

On the other hand, if the judgment in step (10) is NO, wait for a timer interrupt (11), and if YES, read the pointing device coordinate value (12) and judge whether there is a difference from the previous coordinate value. 13), if No, return to step (10); if YES, save the coordinate values 14), and display the cursor (15).

Next, determine whether it is a select area 16), YE
If S, proceed to step (19) and later; if No, determine whether it is a subwindow creation area (17); if No, return to step (lO); if YES, insert the subwindow (18), then step (17). Return to 3).

On the other hand, if the judgment in step (16) is YES, judge whether it is a separate menu or not (19), and if No, in step (19),
Return to lO), and if YES, turn the arrow cursor OFF
(20), issue a select change interrupt (21), wait for a command response (22); if YES, move the arrow cursor to N L (23) and return to step (10).

On the other hand, as shown in FIG. 11(b), the main CPU 33 checks the window at the cursor position (31) and determines whether there is a window (32). If NO, executes another process and displays the pop window row. If YES, issue pop-up menu command 134).
Waits for a command response (35). If YES, a pop-up window is created (36) and pop-up menu command 2 is issued (37). Next, wait for a select change interrupt (38), if No, proceed to step (41) and after, if YES, execute color change (39), issue a response command (40), and step (41).
Return to 38).

On the other hand, if the judgment in step (38) is No, it is necessary to judge whether a subwindow interrupt has occurred (41), YE.
If S, return to step (33); if No, right key O
Please judge whether it is an execution interrupt indicating FF42), YE
If S, delete the pop-up window44), issue a response command45), and execute the command46)
, ends the process.

However, if the judgment in step (42) is No, press the right key O.
43), N
If YES, proceed to another process; if YES, delete the popup window 47) and issue a response command 48
), the process ends.

Next, processing operations of the 5C5I controller 3 and the serial interface 10 of the dual port memory 11 will be explained.

The dual port memory 11 is connected to the printer 2. Because it is used for scanner 1, the capacity is much larger than the dual port memory 12 for CRT display 4, and when outputting one A4 size sheet at a pixel size of 400 dots per inch, it takes approximately 2M bytes. Capacity is required. Therefore, at present, 16 dual port memories using 1M bit chips are required. 256
If we assume a bus width of 16 bits in a 1x4 configuration, we will have 8 memory blocks that cannot be accessed simultaneously. Therefore, six memory blocks are required for B4 size and eight memory blocks for A3 size. When outputting to a printer, the SC3I controller 3 first requests data to the serial interface 10. Since there is no data yet, the serial interface 10 requests the memory controller 13 to perform a read transfer cycle. The memory controller 13 performs memory refresh, c
A read transfer cycle is performed during pu access, etc., and a response signal is sent back to the serial interface 10. Since data already exists in the serial port of the dual port memory 11, the serial interface 10 outputs a serial clock and a data enable signal to read and store data from the serial port of the dual port memory 11. Since the read data is 16 bits, the data is divided into 8 bits and transferred to the SCSI controller 38. As the data is read out in this way, the serial interface 10 counts how many data have been read out, and at the same time it reads out all the data from the serial port of the dual port memory 11, it sends the next address to the memory controller 13. A read transfer cycle request is made to transfer the data to the serial port. The memory controller 13 performs a read transfer cycle to the dual port memory 11 with a shift of the number of serial buffers.

If the range of one memory block is exceeded, a read transfer cycle is performed to the next memory block. Also, when writing data from scanner 1, first 5cs
r controller 3. Serial interface 10. Data flows to the dual port memory 11, but if nothing is done, it is not known whether writing to the first line buffer is in read mode or write mode, so a pseudo write transfer cycle is performed for each memory block before every write. The memory controller 13 performs this. This causes the write enable signal (WE signal) to go LOW at the fall of the row address strobe signal (RAS signal), and the DT double signal S
Set the E signal to HIGH. In a normal write transfer cycle, the SE signal is set to LOW. In the read transfer cycle, the row address strobe signal (RAS signal) is set to LOW, and the write enable signal (WE times signal is set to LOW).
OW, DT double signal LOW. In this way, data transfer is performed after the dual port memory 11 is ready,
The serial interface 10 counts when the serial port buffer is full and requests a normal write transfer cycle from the memory controller 13. The memory controller 13 performs a write transfer cycle, then determines the address of the next write transfer cycle, and
If it exceeds the range of a memory block, enable the next memory block first. In this way, image data is read into a plurality of memory blocks.

Next, the operation of the image compression/expansion device 15 shown in FIG. 1 will be explained.

One side of the memory controller 13 is memory controller 0-1.
3, and the other end is connected to the bus width adjustment device 16.

The memory controller 13 has registers that determine image bits, number of main scans, number of sub-scans, left offset, transfer start address, and transfer direction.
Data is read and written sequentially word by word. Since the image is a bit image, unnecessary data may be generated at the left and right edges. Writing to the dual port memory 11 is performed by using the write bar bit function to set the data bit to be masked to LOW when the RAS signal falls. The leftmost mask data is determined by the left offset register, but the rightmost mask data is more threatening than the left offset register and the main scanning number register. When the image reaches the right edge, it automatically moves to the left edge of the next line. In addition, there are two address systems for the dual port memory 11 for each 8-bit data, and when the transfer address is an odd number, the address of an even number byte is "1" more than the address of an odd number byte. At this time, the odd and even bytes of the data are inverted, so that even if the transfer start address or pitch is an odd number of bytes, one word of 16 bits of data can be transferred in one transfer. In this way, the image compression/expansion device 15 exchanges data with the memory controller 13, and the image compression/expansion device 15 includes registers for commands that determine the number of main scans, the number of sub-scans, the left offset number, compression or expansion, etc. . In this way, the compressed data is passed to the bus width adjustment device 16, and the 16-bit data is converted into 32-bit data and is transferred to the DRAM 31 through DMA processing by the memory controller 32 equipped with a DMA controller.
In the case of expansion, the expanded image data is written to the dual photo memory 11 in the opposite direction. In addition, if a dual port memory 11 with an arithmetic function is used, the column address strobe signal (CAS signal) and WE double signal are set to LOW when the RAS signal falls, and the arithmetic mode is set using the address line. It is possible to perform arithmetic processing such as AND, OR, EXCLUSIVE OR, etc. on the obtained data 3.

〔Effect of the invention〕

As explained above, the present invention is provided with a pseudo cycle execution means for executing a predetermined pseudo write transfer cycle for each image memory block prior to a data write cycle for each image memory block. Controllers can now be managed and devices that process visual data can be
Dual port memory can be accessed independently of PU management. Therefore, conventional visually processable information I
This has an excellent effect of significantly improving the image data transfer processing in the A-processing device.

[Brief explanation of drawings]

FIG. 1 is a system block diagram illustrating the configuration of an information processing device showing an embodiment of the present invention, and FIG. 2 shows an example of inversion processing of the most significant bit of the address line of the sub-CPH shown in FIG. 3(a) to 3(h) are detailed block diagrams explaining the configuration of the arbiter shown in FIG. 1, and FIG. 4 shows the peripheral circuit configuration of the arbiter shown in FIG. The block diagrams to be explained, FIGS. 5 and 6 are flowcharts to explain an example of the startup processing procedure of the sub CPU shown in FIG. 1, and FIG.
Block diagram explaining connection relationship with 10 devices, No. 8
The figure is a timing chart explaining the operation of FIGS. 3(a) to (h), and FIGS. 9(a) to (C) illustrate an example of the cursor/window processing procedure in the information processing apparatus according to the present invention. Flowcharts, FIGS. 10(a) and (b) are flowcharts illustrating an example of the dragging processing procedure by the sub CPU and main CPU in the information processing apparatus according to the present invention, and FIGS. 3 is a flowchart illustrating an example of a pop-up menu display processing procedure in the information processing apparatus according to the present invention. In the figure, 9 is a sub CPU, 13 is a memory controller, 1
4 is an arbiter, 16, 37.40 are bus width adjustment devices, 31 is a DRAM, 32 is a DMA1, 33 is a main CPU, and 38 is an SCS I ink face. (a) Figure (b) Process (C) Main CPU window ttXe process (a) Figure 0 (b)

Claims (1)

[Claims] A plurality of image memory blocks each having a serial port and a random port and dual port memories that can be accessed independently from both ports are arranged, and a memory controller connected to a system bus controls access to the image memory blocks. What is claimed is: 1. An information processing device to be controlled, comprising pseudo cycle execution means for executing a predetermined pseudo write transfer cycle on each of the image memory blocks prior to a data write cycle on each of the image memory blocks.