JPH03180958A - Information processor - Google Patents

Abstract

PURPOSE:To allow a memory access controller to be a resource to relax the restriction of bus cycle design by temporarily interrupting an output bus cycle during the period of a read modified write mode or at the time of switching a reading mode and a writing mode in an input bus when a response from an output bus exists. CONSTITUTION:A bus cycle control means 14 included in the information processor restarts the bus cycle while temporarily interrupting the output bus cycle during the period of the read modified write mode or at the time of switching the reading mode and the writing mode in the input bus when a response from the output bus 43 exists. Consequently, the memory controller 13 to be the resource can executes data processing of respective devices in a normal bus cycle.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing apparatus that executes data processing of each device while adjusting bus rights between a CPU and a direct memory access controller connected to a system bus. It is something.

[Conventional technology]

Conventionally, when performing DMA control in this type of device, the data and address buses are shared between the CPU and the DMA transfer hardware, so it is necessary to adjust the bus ownership. The transfer methods 1) and (2) are adopted.

(1) A method in which transfer is performed using the time when the CPU is not accessing the bus (cycle steal method).

(2) A method in which the DMA control circuit has priority and the CPU is stopped for transfer.

Of these, method (2) is further subdivided into a method in which control is returned to the CPU for each byte of transferred data (byte mode), a method in which control is returned to the CPU for each byte of transfer data, and a method in which DMA is used while a data request is received from an I10 device.
There are two types of methods: a method in which the control side continues to hold the right (continuous mode), and a method in which the DMA side holds the right until the transfer of the required number of bytes is completed (burst mode).

(Problem to be Solved by the Invention) By the way, some of the main CPUs used in this type of device have read mode and write mode in one bus cycle, such as the read-modify write cycle of the TAS instruction. In some cases, it is necessary to design a memory controller to support this bus cycle, which poses the problem of complicating the memory circuit configuration and making bus access control difficult.

This invention was made in order to solve the above problems, and temporarily interrupts the output bus cycle when there is a response from the output bus during read modify write mode, and when the input bus switches between read and write motes. It is an object of the present invention to provide an information processing device that can significantly relax the bus cycle design restrictions imposed by the memory access controller, which is a resource, by interrupting the bus cycle.

[Means for Solving the Problems] The information processing device according to the present invention temporarily interrupts the output bus cycle when in the read modified write mode or when there is a response from the output bus, and when switching between reading and writing on the human-powered bus. A bus cycle control means is provided for restarting the bus cycle without interrupting it.

[Effect]

In this invention, the bus cycle control means is in the read modified write mode or when there is a response from the output bus, and when switching between read and write modes on the human-powered bus, the bus cycle control means does not temporarily suspend the output bus cycle and restarts the hash cycle. However, the memory controller, which serves as a resource, enables data processing with each device in a normal hash cycle.

〔Example〕

FIG. 1 is a system block diagram illustrating the configuration of an information processing apparatus showing an embodiment of the present invention. Reference numeral 1 denotes a scanner that manually scans still images. 2 is a printer that outputs the print result. A 5csr controller 3 inputs and outputs data to and from the scanner 1 and printer 2. 4 is a high-definition CRT display, 5 is an interface, and 6 is a pointing device for specifying coordinate information, icons, etc. by specifying 2 keys. An interface (I/F) 7 processes coordinate information etc. from the pointing device 6. 8 is memory (static RAM), sub CPU
Stores 9 program data. A serial interface 10 inputs and outputs data on the serial port side of the dual port memory (dual port RAM) 11, and has a built-in timer for periodically referencing the state of the pointing device 6. 11 is a dual port memory for a scanner and printer having a random photo and a serial port, 12 is a dual port memory for the CRT display 4, and 13 is a memory controller for refreshing, serial reading, and serial writing of the dual port memory 11.12. , pseudo write transfer tying, CPU access and two-dimensional DMA. 14 is an arbiter (arbiter), and sub CPU 9. Main cpu33
．． DMA controller (DMAC) Controls the adjustment of bus ownership of 13, and also controls sub CPU 9 and main CPU 3.
Performs the interrupt huntshake in step 3. 15 is an image compression/expansion device that compresses/expands image data. Reference numeral 16 denotes a bus width adjustment device that adjusts the compression code of the image compression/decompression device 15 to the bus width of the bus 44 and outputs data. A device 17 performs XY conversion on the image data. A device 18 processes thinning and interpolation of image data. Buffers 19 to 21 drive the bus.

22 is FROM, which stores a boot program and interrupt vectors when the power is turned on. 23 is a static RAM used at startup, and 24 is a device that manages time and stores system management information even when the power is turned off. 2
5 is a counter for switching processes and measuring time.

26 is an interrupt controller that outputs a vector when an interrupt occurs. 27 is an interface that supports serial communication. 28 is a modem connected to a public line, and 29 is an interface for inputting keys from a keyboard 30. 31 is dynamic RA
M (DRAM) stores program data on the system side. A memory controller (DMA controller) 32 controls refresh of the DRAM 31 and DMA with each device with the memory. 33 is a main CPU, and 34 is a device which performs address decoding, interrupt control, and control of each control line. 3
5 is a boat with built-in fonts of various typefaces and kana-kanji conversion dictionaries, etc., and 36 is an interface, IEEE802
．． 3 108ASE5 (so-called ETHRNET) is supported. 37 is a device constituting the bus width adjustment means according to the present invention, and is an interface between an 8-bit input/output SC3I controller (SC3I controller) 3B (constituting a direct memory access device) and a data bus 45 having a 32-bit data width. I do.

39 is a hard disk with 5CSII/F, 40 is a bus width adjustment device, and 41 is an interface device, which interfaces between the floppy disk controller and the bus 45. 42 is a 3.5-inch floppy disk drive, 43 is a bus with a data width of 16 bits, 44.45 is a bus with a data width of 32 bits, 4
6 is a bus having a data width of 16 bits, and 47 is a bus having a data width of 16 bits that can be accessed only from the sub CPU 9. The polarity of the most significant bit of this address line is set to the polarity of the address line coming out from the sub CPU 9. It is configured so that it can be reversed. In the information processing device configured in this manner, the arbiter 14 constituting the bus cycle control means is configured to operate in read modified write mode or when a response from the output bus (for example, the image bus 43) is present, as will be described later. When switching between read and write modes, the output bus cycle is temporarily interrupted and the bus cycle is restarted, and the memory controller (DMAC13 in this embodiment), which serves as a resource,
) allows data processing with each device using normal bus cycles.

FIG. 2 is a circuit block diagram showing an example of the IA process for polarity inversion of the most significant bit of the address line of the sub CPU 9 shown in FIG. Based on this, a Q output is sent to an exclusive OR gate (EX-OR circuit) 101.

3(,) to (h) show the arbiter 14 shown in FIG.
FIG. 1 is a detailed block diagram illustrating the configuration of FIG.

In these figures, 201 to 205 are EX-OR circuits, 206 is an inverter, 207 to 211 are EX-OR circuits, 212 is an inverter, 213.214 is a NAND circuit, 215 is an inverter, 216 is an AND circuit, and 217
is a NAND circuit, 218 is an AND circuit, 219 is a NAN
D circuit, 220 is an AND circuit, 221 to 223 are reset terminal @JK Philip flop (JKFF), 22
4 is a NOR circuit, 225 is an impeller, 226.227 is a NOR circuit, 228 is an inverter, 229 to 232 are N
OR circuit, 233 is OR circuit, 234, 235 are D flip-flops (DFF), 236, 237 are inverters, 23B is NOR circuit, 239 is DFF, 240 is JK
FF, 241 is an inverter, 242 is a NAND circuit, 2
43 is an AND circuit, 244 is an inverter, 245 to 24
7 is DFF, 248 is NAND circuit, 249 is AND circuit, 250 is JKFF, 251.252 is DFF, 25
3 is an AND circuit, 254 is an inverter, 255 to 257
is DFF, 258 is NAND circuit, 259 is AND circuit, 260 is JKFF, 261.262 is DFF, 263
．． 264 is a DFF, 265 to 267 are NAND circuits, 2
68 is an inverter, 269.270 is a NAND circuit, 2
71 is an inverter, 272273 is a NAND circuit, 27
4 is inverter, 275.276 is DFF, 277~2
79 is a NAND circuit, 280 is an inverter, 281.2
82 is an AND circuit, 283 is a NOR circuit, 284 is a 3-state buffer, 285 is an inverter, 286 is a NOR circuit
circuit, 286 is a NOR circuit, 287 is an inverter, 28
8 is a NOR circuit, 289 is an inverter, 290.291 is a NOR circuit, 292 is a 3-state buffer, 293 is an inverter, 294 is a NOR circuit, 295 is an inverter,
296 is a NOR circuit, 297 is an inverter, and 298 is an NOR circuit.
OR circuit, 299 is an inverter, 300 is a NOR circuit,
301 is an inverter, 302 is a NOR circuit, 303 is an N
OR circuit, 304 is 3-state buffer, 305.30
6 is an inverter, 307 to 310 are NOR circuits, 311
is an AND circuit, 312 and 313 are NOR circuits, 314 is a 3-state buffer, 315 to 326 are OR circuits, 32
7 is AND circuit, 328 is 5RFF, 329 is NAND
AND circuit 0 is an OR circuit, 331 is a NAND AND circuit 2 is an OR circuit, 333.334 is a NAND AND circuit 5
, 336 are AND circuits, and 337, 338 are 5RFFs.

FIG. 4 is a block diagram illustrating the peripheral circuit configuration of the arbiter 14 shown in FIG. It is a path transceiver.

Next, the start-up processing operation of the sub CPU 9 etc. shown in FIG. 1 will be explained with reference to FIGS. 5 and 6.

FIGS. 5 and 6 are flowcharts illustrating an example of the procedure for starting up the sub CPU 9 shown in FIG. 1.

Note that (1) to (9) and (11) to (25) indicate each step.

When the power is turned on, the main CPU 33 first boots up, inputs the values of the stack pointer and program counter at the time of reset from the FROM 22, and performs startup processing.

At this time, the sub CPU 9 displays a cursor on the dual port RAM 11 based on the signal from the bonding device 6, controls the SCSI controller 3, and controls the scanner 1. The steps include transferring image signals to the printer 2 and performing an interrupt handshake with the main CPU 33 via the arbiter 14.
In step 1), check the size of the entire program and set the number of words to be transferred. Next, the transfer start address when viewed from the main CPU 33 of the dual port memory 12 is set (2).

Next, data including programs and the like is transferred from the FROM 22 or the DRAM 3T to the dual port memory 12 (3). Next, a data sum is performed to add the data value to a certain register or memory (4), and it is determined whether the transfer is completed, that is, whether the number of transfers remains is "O" (5), and if NO, step Return to (3) and YE
If S, the added data value (checksum) is transferred (6).

Next, the JSTART signal is given to the arbiter 14, and the sub CPU 9 to which the reset signal has been applied until now starts (7).

Next, the sub CPU 9 manually reads the stack pointer and program counter from the dual port memory 12, and then transfers the program loaded in the dual port memory 12 to the static RAM (SRAM>8) according to the flow shown in FIG. The interrupt vector of sub CPU 9 is loaded into static RAM.
Invert the most significant bit of the address so that it switches to 8.

Next, wait for an ACK interrupt to occur (8), and when the interrupt occurs, write the interrupt response command J I QACK to the 18M register (9), and end the process.
The process moves on to processing by the sub CPU 9.

The size of the entire program is checked and the number of words to be transferred is set (11). Next, the dual photo memory 12
The transfer start address as seen from the main CPU 33 is set (12).

Next, data including programs and the like is transferred from the FROM 22 or DRAM 31 to the dual port memory 12 (13). Next, a data sum is performed to add the data value to a certain register or memory (14), and it is determined whether the transfer is completed, that is, whether the number of transfers remains is "0" (15). If NO, step Return to step (13), if YES, determine whether the checksum is OK or not (16), if NO, proceed to step (23) and onwards.
If ES, data is written to the inversion register (↓7
), determine whether the checksum of SRAM8 is OK (18), if NO, proceed to step (23) and onwards, and Y
If it is ES, write the normal status to the VRAM buffer (19) and send the interrupt command KIQA to the 18M register.
Write CK (20). Wait for the ACK interrupt to occur (21), and when the interrupt occurs, write the interrupt clear command KIQCLR to the 18M register (22)
), the process ends.

On the other hand, if NO in steps (16) and (18), V
Write error status to RAM buffer (23)
, writes the interrupt command KIQACK to the 18M register (24). Wait for ACK interrupt to occur2
5) When an interrupt occurs, write an interrupt clear command KIQCLR to the 18M register (25) and end the process.

Specifically, the most significant bit of the address is input to one side of the EX-OR circuit 101 shown in FIG. 2, and the output of the flip-flop 102 is input to the other side.
By inverting the output of 2, the polarity of the most significant bit of the address is switched. Next, the notification that the program transfer has been completed is written to the communication buffer with the main CPU [J33 provided in the dual port memory 12, a KIACK signal is given to the arbiter 14, and the main CPU
This is done by applying an interrupt signal to 33. Main cpu3
3 receives an interrupt signal from the arbiter 14 (PUTJ I
The ACK is sent to the arbiter 14 to interrupt the sub CPU 9. The sub CPU 9 sends a K I Q CL R signal to the arbiter 14 as an interrupt clear signal, and the sub CPU
The initial operation of step 9 ends.

Next, by transferring the bitmap data to the dual port memory 12, the bitmap image can be displayed on the CRT display 4 through the interface 5.

Next, the O3 (operating system) and application program (AP) are transferred from the hard disk 39 to the dynamic RAM 31, but in this system, the DMA controller 32 and bus width adjustment device 37 are normally located between the main CPU 33 and the SCS I controller 38. 8-bit width data transfer is being performed, but when a DMA transfer command is issued and a request is output from the SC3I controller 38 and manually input to the bus width adjustment device 37, the bus width adjustment device 37 performs the DMA transfer. When becoming a remote mode and writing data from the dyna main drive RAM 31 to the hard disk 39, the width adjustment device 37
outputs a DMA request to the DMA controller 32.

The DMA controller 32 requests bus ownership from the main CPU 33, and when the main CPU 33 releases the bus,
The DMA controller 32 takes control of the bus and writes 32-bit width data to the bus width adjustment device 37. The bus width adjustment device 37 cancels the DMA request, thereby also releasing the DMA controller 32 and the main CPU 33 taking control of the bus again.

On the other hand, the bus width adjustment device 37 decomposes 32-bit width data into 8-bit width data and writes the data to the SCSI controller 38 when a request is output. When the four writes are completed, there is no more data in the bus width adjustment device 37, so the bus width adjustment device 37 again sends the DMA request to the D.
The signal is output to the MA controller 32 and the above operation is repeated.

The 5CSI controller 38 transfers data to the pigeon disk 39 in accordance with the SCSR standard. A series of operations are performed until data of a fixed block length is transferred. The bus width adjustment device 37 is the DM silicon roller 32
When the DMA transfer end signal DONE is generated from 5CSI controller 38 or the transfer end signal is generated from 5CSI controller 38, DONE is automatically activated.
Exit MA transfer mode, enter normal mode and transfer to 5C5I
It becomes possible to communicate between the controller 38 and the main CPU 33. Furthermore, when writing data from the hard disk 39 to the dynamic RAM 3+, data from the SCSI controller 38 is written to the bus width adjustment device 37 four times before the bus width adjustment device 37 outputs a DMA request to the DMA controller 32. The only difference is that the direction of data transfer is reversed, and the other operations are the same as those for writing to a disk.

In this way, by providing the bus width adjustment device 37, even if there is a device in progress of DMA transfer, the main CPU 3
3 can execute programs by taking control of the bus between transfers without being constantly held by the DMA controller 32.

However, the DMA10 device, in this example, the SC
In the 3I controller 38, a problem occurs when the read signal and the write signal are processed by a simple OR operation from the CPU and the bus width adjustment device 37. The read signal and write signal output from the bus width adjustment device 37 are D
Although only generated during MA, read signals and write signals output from the CPU are output for other Ilo's even during DMA when the CPU holds the bus right. Naturally, this has a different timing from the read signal and write signal generated from the bus width adjustment device 37, so there is a possibility that the SC3I controller 38 will malfunction. To prevent this, there is a method of providing a signal indicating that DMA is in progress and switching the signal between the bus width adjustment device 37 and the CPU, and a method of switching the signal between the bus width adjustment device 37 and the CPU. There is a method of inputting read/write signals, but the latter method is optimal in order to satisfy the timing.

FIG. 7 is a block diagram illustrating the connection relationship between the bus width adjustment device and the DMA110 device, where 401 is the bus width adjustment device, 402 is the DMA110 device, and 40
3.404 is ○R get, and 405.406 is AND gate.

DMA I10 device 402 and bus width adjustment device 4
The DMA transfer of 01 is performed using the REQ signal and the ACK signal. Normally, CPU access is done by chip select signal, read signal, write signal or DMAT/○ device 402. Both bus width adjustment devices 401 are manually operated, and DMA and Al
Reading and writing to 10 devices 9 402 are accessed using 8 bits. DMA command is issued and DMA10 device 4
When the REQ signal is output from 02, the bus width adjustment device 401 becomes a DMA transfer mode, and the system bus is
Data is transferred using 2 bits. Bus width adjustment device 40
1 returns an ACK signal upon receiving the REQ signal, but at the same time, it changes the DMARD signal or DMAWR signal to LOW level depending on the transfer direction and sends the RDB signal and WRB signal to the DMA110 device 402 via the AND gate 405406. If the system bus is not occupied by the DMAC, the CPU may issue read signals and write signals for each I10, and the read signals and write signals are simply OR1 with AND gates 405 and 401, DMAAl
If the RDB signal and WRB signal of the 10 device 402 are manually input, the DMA transfer may not be performed normally. Therefore, if the chip select signal, read signal, and write signal are ANDed by OR gates 403 and 404 and then ORed by AND gates 405 and 406, no malfunction will occur.

Of course, each of these gates is connected to the bus width adjustment device 37.
It can also be built into.

Also, the bus width adjustment device 40. The operations of the floppy disk controller 4i and the 3.5-inch floppy disk drive are substantially the same.

The memory controller 32 has three sets of DMA channels, and parallel transfer between a hard disk and a floppy disk is also possible. Further, the operation of the arbiter 14, which controls the access of the main CPU 33 and the sub CPU 9 to the dual port memory 1112 at the same time, will be explained with reference to FIG. 3(a).

EX-OR circuits 201 to 205 are used for address selection of the dual port memory 11.12 when viewed from the sub CPU 9, and EX-OR circuits 207 to 211 are used for main CPU
Dual port memory 11.12 when viewed from U33
used for address selection. Unnecessary gates are connected so that the output is HIGH.

Boats KLVL1 to 5 of EX-OR circuits 201 to 205
and boat JLVL of EX-OR circuits 207 to 211
For I~5, manually set the level of polarity opposite to the polarity of the address to be selected, and for boats KAA1~5 and JAAI~5.
A bit is connected to determine the address to be selected. As a result, when the sub CPU 9 outputs the address of the dual port memory 11.12, the EXO
The outputs of R circuits 201 to 205 become HIGH,
Also, since the address strobe signal KASB becomes LOW, the output of the inverter 206 becomes HIGH, and the NA
The output of the ND circuit 213 becomes LOW. As a result, NO
The output of the R circuit 217 becomes HIGH, and at the rising edge of the CLK signal, the Q output of the JKFF 222 becomes HIGH1 inverted Q output inverted LOW. The NOR circuit 217 also outputs HIGH even when the signal KLC3B for selecting the memory controller 13 becomes LOW.

Similarly, from the main CPU 33 to the dual port memory 1
When address 1.12 is output, EX-OR circuit 2
All the outputs of 07 to 211 become HIGH, and the address strobe signal JASB becomes LOW, so the output of inverter 212 becomes HIGH, and the NAND circuit 2
The output of No. 19 becomes LOW. As a result, NAND circuit 2
The output of 19 becomes HIGH, the CLK signal rises, and the Q output of JKFF223 becomes HIGH1 inverted Q output inverted L
OW becomes. The NAND circuit 219 also remains high even if the signal JLCSB for selecting the memory controller 13 goes low.
It becomes IGH output. Also, the memory controller 13
When the LBRB signal is set to LOW to perform MA transfer, the inverter 215 becomes HIGH, and when the CLK signal rises, the Q output of the JKFF 221 becomes HIGH1 inverted Q output inverted LOW. In this way, JKFF221~
223 inverted Q output S3. S6. S11 or LOW at the same time
, the output S of the NOR circuit 227.232
8 and the output ■ become HIGH, and as a result, the NOR circuit 22
4 output @ is LOW, NOR circuit 229 output ■ is LOW
It becomes W.

That is, only the output ■ becomes HIGH, and the outputs ■ and output ■ become LOW.

Similarly, output 33. S6 is LOW, output Sll is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW.

Similarly, output S3. Sll is LOW, output s6 is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW.

Similarly, output S6. Sll is LOW, output s3 is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW. Also, when output S3 is LOW alone, when output s6 is LOW alone, only output ■ is LOW.
Therefore, when the output s11 is LOW alone, only the output ① becomes LOW. In other words, the priority order of the arbiter 14 is fixed, and the output is defined as Sll>S6>S3. In this way, when any of the outputs ■, ■, ■ becomes HIGH, the output S14 of the OR circuit 233 also becomes HIGH, and at the falling edge of the CLK signal, the DFF 234 latches the output S14 by the inverter 236 and becomes a Q output. Output S15 becomes HIGH. Inverted Q output is L
OW, and since this is connected to the inverted S output of DFF235, S16 becomes the inverted Q output of DFF235.
becomes LOW immediately. As a result, the NOR circuit 226
The output S7 of will be at the same level as the output ■, and if the output ■ is HIGH, the output S7 will also be HIGH.
Even if the output S6 becomes LOW, the output S of the NOR circuit 227
8 will no longer go HIGH. In other words, the output ■
becomes HIGH and the inverted Q output s1 of DFF235
6 becomes LOW, NO even if the output S6 becomes LOW.
The R circuit 224 prevents the output (2) from becoming LOW.

This provides stable access. Similarly, NO
The output S13 of the R circuit 231 is output by the NOR circuit 230.
If either the output ■ or the actual output is HIGH, it becomes HIGH, and even if the output Sll becomes LOW, the NOR circuit 232
The output ■ will not become HIGH. That is,
Output ■, when the actual output becomes HIGH and the output 316, which becomes the inverted Q output of DFF 235, becomes LOW, the output S
Even if the output becomes L○W, the NOR circuits 224 and 229 prevent the output ■ and the output ■ from becoming LOW. in this way,
Once a lower priority run cycle is started, it cannot be interrupted by higher priority inputs until the run cycle is finished. Output Sll, which is the inverted Q output of JKFF223, becomes LOW, output ■ becomes HIGH, and DF
When the output S16, which is the inverted Q output of F235, becomes LOW and an execution cycle begins, the LJB output also becomes LOW due to the inverter 254 in FIG. 3(b). The LJB output is connected to the tri-state input of the address buffer 352 and the tri-state input of the data buffer 353 of the main CPU 33, so that the bus mastership of the bus 43 is held by the main CPU 33. The memory controller 13 uses dual port memory 11.12 according to the address.
and returns a data acknowledge signal LDTKB to the Avita 14. In the arbiter 14, the inverter 271. shown in FIG. 3(e). It is output as a JDTAK signal through NAND circuits 269 and 270. This signal is returned to the main CPU 33, and the main CPU 33 sets the JASB signal to HIGH, thereby completing the cycle. As a result, the output SIO of the AND circuit 220 in FIG. 3(a) becomes HIGH.
, the output S17 of the NOR circuit 238 becomes LOW, the Q output S15 of the DFF 234 becomes LOW, and the inverted Q becomes HI.
It becomes GH. Here, the CLK signal changes from LOW to HIGH.
Then, the output S1 becomes the inverted Q output of JKFF223.
1 becomes HIGH and N.

The output ■ of the R circuit 232 is LOW, and the A shown in FIG. 3(b)
The output LJAS of the ND circuit 259 also becomes LOW, and bus ownership of the image bus is released from the main CPU 33. C
DF at the same time as JKFF223 at the rise of the LK signal.
Output 316, which is the inverted Q output of F235, also becomes HIGH, and output 53S6. The adjustment cycle for each Sll signal begins. Here, output S6 only or output S3. S6 is LO
If W, the sub CPU 9 takes control of the bus as described above, and the data acknowledge signal LDT of the memory controller 13
KB also terminates the bus cycle.

On the other hand, in the arbiter 14, there is a DFF 251 shown in FIG. 3(b).
, 252, 261, 262, and if the main CPU 33 and sub CPU 9 are accessed close to each other, the LA
In order to prevent the SB signal and LDTKB signal from affecting the memory controller 13 and each CPU 9.33 due to delay time, etc., the LJA signal is
The S signal and LKAS signal are separated so that they do not come close to each other. Even if the output ■ becomes LOW and immediately the output ■ becomes HIGH, the Q output of the DFF 261 becomes LOW, the inverted Q output of the DFF 262 starts to become HIG, and the LKAS signal becomes HIGH. The same applies to the LJAS signal. In addition, L'A shown in FIGS. 3(d) to (f)
SB signal, LUDSB signal, LLDSB signal, LRW
signal, LC3B signal and J shown in Fig. 3(C).
DTAK signal, KDTAK signal, JBER signal, KBE
Each of the R signals will not become valid unless either the LJAS signal or the LKAS signal is HIGH. As a result, the main CPU 33 and sub CPU
9, single accesses can be performed at high speed, and accesses in close proximity can be performed safely.

By the way, the JKFF221 is activated by the bus request signal LBRB from the DMA controller 13 on the image bus.
When the output S3, which is the inverted Q output, becomes LOW and the output O becomes HIGH, the JD
TAK signal, KDTAK signal, JBER signal, KBER
All of the signals become valid unless either the LJAS signal or the LKAS signal is HIGH. Thereby, individual access between the main CPU 33 and sub CPU 9 can be performed at high speed, or close access can be performed safely.

By the way, the JKFF 221 is
When the output S3, which is the inverted Q output, becomes LOW and the output ■ becomes HIGH, the D
The inverted Q output of FF239 goes high at the rising edge of the CLK signal.
IGH and LBG, which is the output of the NAND circuit 242
The B signal becomes LOW. This is DMA controller 1
The DMA controller 13 sets the LBGAKB signal to LOW and the LBRB signal to HIGH. As a result, the output of the inverter 241 becomes HIGH, and the Q output of the JKFF 240 becomes LOW. As a result, the LBGB signal becomes HIGH. D
The MA controller 13 starts data transfer and holds the LBGAK signal LOW until the data transfer is finished.

When the data transfer is completed and the LBGAK signal is set to HIGH, the output S2 of the AND circuit 216 shown in FIG. 3(a)
becomes HIGH, and the output S17 of the NOR circuit 238 becomes L.
OW, and the output S15, which is the Q output of the DFF 234, is set to LOW. JKFF22 at the rise of CLK signal
The output S3, which is the inverted Q output of 1, becomes HIGH, and at the same time, the output S16, which is the inverted Q output of the DFF 235, also becomes HIGH.
The signal becomes H, the output ■ becomes LOW, and the arbitration cycle begins again. Access to the main CPU 33 is indicated by the JASE signal being LOW in a normal cycle, but in order to synchronize the software of the main CPU 33 and sub CPU 9, a read and write cycle that must not be divided, a so-called read modify write cycle, is performed. be. At that time, from the main CPU33
This cycle is recognized by the CB signal becoming LOW.

This JRMCB signal is manually input to the AND gate shown in Figure 3(a), and the JASB signal becomes HIGH.
In a normal cycle, the output 10 becomes HIGH to end the cycle, but when the JRMCB signal is LOW, the cycle is not ended to support the read-modify-write cycle. On the other hand, sub CPU
The 9 side does not have a KKRMCB signal and supports the following processing.

The KRW signal is HIGH1, that is, KA in the read cycle.
The SB signal goes LOW, then the KUDSB signal or KLDSB signal goes LOW, 1. The dual port memory 11 or dual port memory 12 is read, and the memory controller 13 reads LDTAK.
The B signal is set to LOW, and the arbiter 14 outputs it as a KDTAK signal. As a result, the KUDSB signal or KLDSB signal becomes HIGH, and the KASB signal becomes LOW.
While it remains OW, the KRW signal becomes LOW and the KUDS
The B signal or KLDSB becomes HIGH, and data is written to the dual photo memory 11 or dual port memory 12. The memory controller 13 again sets the LDTAKB signal to LOW. As a result, the KUDSB signal or KLDSB signal including the KASB signal becomes HIGH, and the cycle ends.

On the other hand, the memory controller 13 transfers all cycles to LA.
The period when the SB signal is LOW, the memory controller 13
It does not itself support read-modify-write cycles. For this reason, DFF245-247. JKF
F250. LDTAK once by NAND circuit 248
The B signal goes LOW, and the KRW signal goes from HIGH to LOW.
When switched to W, the LKAS signal is set to LOW once, that is, the LASB signal is set to HIGH once.

When the LDTAKB signal becomes LOW, the inverter output LDT of the inverter 271 shown in FIG. 3(C) becomes HIGH.
It becomes H, and the Q7 output of JKFF250 becomes HIGH. When KRW goes from HIGH to LOW, DFF246
．． When the Q output of 247 is HIGH, the inverted Q of DFF245
Since the output becomes 1 (IGH), the LKAS signal is LOW and the LASB signal is HIGH while the CLK signal rises twice.
Becomes IGH. The arbiter 14 thus supports two types of read-modify-write cycles, and does not change the rights to the image bus during these cycles. Also,
The LASB signal always goes LOW twice.

The arbiter 14 also supports interrupt handshaking between the main CPU 33 and sub CPU 9.
When the signal JD1 shown in FIG. 3(g) is set to LOW and the signal JRW and JC3B are set to LO4W, the DFF 263.3 shown in FIG. 3(c). The signal 264 and the NAND circuit 265 cause the JJB signal to go LOW from one rising edge to the next rising edge of the CLK signal, and the OR circuits 321 and 315 in FIG. 3(g) turn the JJB signal LOW.
QACK (g becomes LOW. As a result, OR circuit 3
The output of K 30 becomes LOW, the output of NAND circuit 331 becomes HIGH, and the output of NAND circuit 329 becomes LOW.
The INTB signal becomes LOW, and this signal is sent to the sub CPU9.
It becomes an interrupt signal for The sub CPU 9 sets the KDI signal shown in FIG. 3(g) to LOW and outputs the KRW signal and KCSB.
When the signal is set to LOW, the DFF2 shown in Fig. 3(c)
75.276 and the NAND circuit 279, the KKB signal is LO from the rising edge of the CLK signal to the next rising edge.
W, and the KIQACK signal becomes LOW by the OR circuits 326 and 322 in FIG. 3(h). As a result, OR
The output of the circuit 332 becomes LOW, and the NAND circuit 333
The output of JINTB becomes HIGH, and the JINTB signal, which is the output of the NAND circuit 334, becomes LOW.
The B signal becomes an interrupt signal to the main CPU 33, and at the same time the KINTB signal, which becomes the output of the NAND circuit 329, goes H.
IG) (and clear the interrupt signal. The other party's CP
To clear only your own interrupt signal without interrupting U, use JD instead of main CPU33 or JDI signal.
If the sub CPU 9 sets the KD2 signal to LOW instead of the KDI signal, the JIQCLR signal, KI
The QCLR signal becomes LOW, clearing the interrupt. Also, the signal JD3. Signal KD
3 is LOW, JRW signal and JCSB signal are LOW.
, KPW signal, and KCSB signal are LOW, JMS
KST signal, KMSKST signal becomes LOW, 5RF
The Q output of F328.337 becomes HIGH, and the outputs of OR circuits 330 and 332 no longer become LOW.
Interrupt signals will no longer be generated. The interrupt can also be canceled by setting the JD4 signal and KD4 signal LOW, the JRW signal and JC3B signal LOW, and the KRW signal and KCC3B signal LOW. Also, from the main CPU33, JD5
If the signal, JRW signal, and JC3B signal are LOW, then K
The RESB signal can be set to HIGH, and if this is used as a reset signal for the sub CPU 9, the sub CPU 9 can be started from the main CPU 33. JD6 signal,
By setting the JRW signal and the JC3B signal to LOW (see FIG. 8), the sub CPU 9 can be reset again.

The data transfer process will be specifically explained below, taking as an example a case where a window and a cursor are displayed on the CRT display 4 using the dual port memory 12.

Not all areas of the dual port memory 12 are used for display, and some areas can be used as completely free RAM. This dual port memory 12
Since it can be accessed from both the main CPU 33 and the sub CPU 9, it is ideal as a communication buffer. The arbiter 14 is used to interrupt the other party, and the status of the command or response at that time is exchanged in the communication buffer in the free area of the dual boat memory 12.

In this system, the cursor is displayed on the sub CPU 9, and the main CPU 9 is responsible for creating windows and rewriting the window contents.
PO33 is responsible for this.

Therefore, when using the main CPU 33 or VRAM, write the window rewriting request command and the window coordinates in the communication buffer and send it to the arbiter 14.
It issues an ACK signal command and interrupts the sub CPU 9. The sub CPU 9 receives the window rewrite request command from the communication buffer using the KINTB signal, which is an interrupt signal, and turns on the busy flag. Next, window 4
It takes the coordinates of va and performs a clipping operation on the window where the cursor is displayed. As a result, if there is an overlap between the cursor and the window that the main CPU 33 is attempting to rewrite, the sub CPU 9 erases the cursor and restores the original image to that area. And arbiter 1
Issues a KIQACK signal to main CPU3.
Generate an interrupt signal at 3 and a JINTB signal at 8. The main CPU 33 rewrites the window upon receiving an interruption in response to this window rewriting command. If there is no overlap between the cursor and the window, do not erase the cursor and use KIQACK.
Issue a signal. When the main CPU 33 finishes rewriting the window, it writes an end rewriting command in the communication buffer and sends a JIQACK signal to the arbiter 14.
A QACK signal is issued to cause the sub CPU 9 to generate a KINTB signal as an interrupt signal. The sub CPU 9 thereby turns off the busy flag and sends a K to the arbiter 14.
The main CPU issues the IQACK signal and receives the generated JINTB signal interrupt as a response to the termination command.

The sub CPU 9 not only processes interrupts, but also displays a cursor in a separate routine, reads the coordinate values of the pointing device every time a timer interrupt occurs on the interface 10, and if there is a difference from the previous one, saves the coordinate values. Look at the busy flag that turns ON10FF in the previous interrupt routine, and if it is ON, clip the rewrite window with the cursor window, if there is an overlap, do not display the cursor, and if there is no overlap and the busy flag is OFF, do not display the cursor. indicate. Cursor display means saving the image in the cursor window and displaying a cursor such as an arrow.
When moving the cursor to another location, the evacuated image is returned and the image is evacuated again at the moved position.

Next, the cursor/window processing operation in the information processing apparatus according to the present invention will be explained with reference to FIGS. 9(a) to 9(c).

FIGS. 9(a) to 9(C) are flowcharts illustrating an example of a cursor/window processing procedure in an information processing apparatus according to the present invention. In addition, (1) to (9), (
11) to (19) and (21) to (26) indicate each step. Hereinafter, the process will be explained sequentially starting from the process shown in FIG.

When the timer interrupt processing occurs, the sub CPU 9 (1)
Read the coordinate values from the pointing device 6 (2
), determine whether there is a difference from the previous coordinate values 3)
, if No, return to step (1), and if YES, save the current coordinate values (4).

Next, determine whether the busy flag is ON or not 5).
If NO, proceed to step (9) and onwards; if YES, take the coordinates of the four corners of the rewrite window (6); then,
Try clipping in the cursor window 7) and determine if there is an overlap 8) If YES, return to step (1); if NO, display the cursor 9) and return to step (1).

On the other hand, the communication interrupt process is as shown in FIG.
Determine whether a window rewrite request has occurred (11), and if YES, turn on the busy flag (11).
2) Take the coordinates of the four corners of the rewriting window (13)
. Next, try clipping in the cursor window 14)
, it is determined whether or not there is an overlap (15), and if No, the process proceeds to step (17) and subsequent steps; if YES, the cursor is deleted (16), a response command is issued (17), and the process ends.

On the other hand, if the determination in step (11) is No, the busy flag is turned off (48), a response command is issued (19), and the process is terminated.

On the other hand, the main CPO 33 sends the coordinates of the four corners of the rewrite window to the communication buffer (21
), issue a window rewrite request command 22), wait for a command response from the sub CPU 9, etc. 23), and when a response is received, rewrite the window (2
4) Issue a command to end window rewriting (
25). Next, 1, the process waits for a command response from the sub CPU 9, etc. 26), and ends the process.

Next, while referring to FIGS. 10(a) and (b), the sub-CP
The dragging process by U9 and main CPU 33 will be explained.

FIGS. 10(a) and 10(b) are flowcharts illustrating an example of a dragging process procedure performed by the sub CPU 9 and the main CPU 33 in the information processing apparatus according to the present invention.

Note that (1) to (18) and (21) to (29) indicate each step.

The sub CPU 9 sends the cursor position to the communication buffer (
1), issues an interrupt indicating left key ON (2), and waits for a command response (3).

Next, it is determined whether it is a dragging command 4), N
If YES, perform another process, if YES, take the window frame size position (5) and move the arrow cursor to 0FFL (6)
, the window frame is displayed in reverse (7). Next, wait for a timer interrupt to occur (8), and when the interrupt occurs, read the coordinate values of the pointing device 6 (9),
To determine whether there is a difference from the previous coordinate values 10),
If No, return to step (8); if Yes, save the coordinate values (11) and change the window frame position (12).

Next, display the window frame (13), determine whether the key is in the OFF state (14), and if No, step (8).
If the answer is YES, the window frame size position is transferred (15), an interrupt indicating that the left key is OFF is issued, and 16L command response is waited for (17). Then,
A command response is issued (18), and the process ends.

On the other hand, as shown in FIG. 10(b), when the interrupt is issued in step (2), the main CPU 33 checks the window at the cursor position (21) and determines whether it is a dragging area (22). The window frame size, position, etc. are sent to the communication buffer (23), and a dragging command is issued (24). Next, it is determined whether there is a command response (25), and if YES, the window frame size and position are taken (26).

Next, the window is rewritten (27) and a window rewriting end command is issued (28). Next, it waits for a command response (29), and when the command response is issued, the process ends.

Next, the pop-up menu display processing operation of the information processing apparatus according to the present invention will be explained with reference to FIGS. 11(a) and 11(b).

FIGS. 11(a) and 11(b) are flowcharts illustrating an example of the pop-up menu display processing procedure of the information processing apparatus according to the present invention. In addition, (1) to (29)
, (31) to (48) indicate each step.

First, the sub CPU 9 sends the cursor position to the communication buffer (1) and issues an interrupt indicating that the right key is ON (2).
. Then, wait for a command response 3),
If YES, it is determined whether it is a pop-up menu command (4), if YES, the pop-up window row is read out (5), and the arrow cursor is turned off (6). Next, issue a response command (a), wait for a command response (8), and if YES, turn on the arrow cursor.
Step 9), check whether the right key is OFF or not 1o), proceed to step (24) and later, turn the arrow cursor OFF,
It is determined whether it is a select area (25), and if YES, the right key is pressed to 0FFL and an execution interrupt is issued (26). Next, wait for a command response 28), Y
If it is ES, turn on the arrow cursor (29) and end the process.

On the other hand, if the determination in step (25) is No, press the right key to issue a non-execution interrupt (27), and proceed to step (28).

On the other hand, if the judgment in step (10) is No, wait for a timer interrupt (11), and if YES, read the pointing device coordinate value (12) and judge whether there is a difference from the previous coordinate value. If the answer is NO, the process returns to step (10); if the answer is YES, the coordinate values are saved 14) and the cursor is displayed (15).

Next, determine whether it is a select area 16), YE
If S, proceed to step (19) and later; if NO, determine whether it is a subwindow creation area (17); if No, return to step (10); if YES, insert the subwindow (18), and step (17). Return to 3).

On the other hand, if the judgment in step (16) is YES, judge whether it is a separate menu (1g), if No, return to step (lO), and if YES, turn the arrow cursor OFF.
L (20), issue select change interrupt 21)
, wait for a command response 22), and if YES, turn the arrow cursor ON L, (23), return to step (lO).

On the other hand, as shown in FIG. 10(b), the main CPU 33 checks the window at the cursor position (31) and determines whether there is a window (32). If N0, executes another process; if YES, Pop-up menu command 1
(34) and waits for a command response (35).

If YES, create a pop-up window 36),
Pop-up menu command 2 is issued (37).

Next, wait for a select change interrupt.38
), if NO, proceed to step (41) onwards; if YES, execute color change 39), issue response command 40), return to step (38).

On the other hand, if the judgment in step (38) is No, it is necessary to judge whether a subwindow interrupt has occurred (41), YE.
If S, return to step (33); if NO, right key O
Determine whether it is an execution interrupt indicating FF42), Y
If it is E or S, the pop-up window should be deleted 44),
Issue the response command 45), execute the command 4
6), end the process.

If the judgment in step (42) is NO, press the right key O.
43), N
If o, proceed to another process; if YES, delete the pop-up window47) and issue a response command48
), the process ends.

Next, 5CSI controller 3 and dual photo memory 1
The processing operation of the serial port interface 10 will be explained.

The dual port memory 11 is connected to the printer 2. Because it is for one scanner, the capacity is much larger than that of the dual port memory 12 for four CRT displays, and when outputting one A4 size sheet at a pixel size of 400 dots per inch, it is approximately 2 MB. capacity is required. Therefore, at present, 16 dual port memories using 1M bit chips are required. 256
It is composed of 4 bytes and has a width of 16 bits, so it is composed of four memory blocks that cannot be accessed simultaneously. Therefore, six memory blocks are required for B4 size and eight memory blocks for A3 size. When outputting to a printer, the SC3I controller 3 first requests data to the serial interface 10. Serial interface 10 also requests memory controller 13 to perform a read transfer cycle since no data is available. The memory controller 13 performs a read transfer cycle during memory refresh, CPU access, etc., and sends a response signal back to the serial interface 0. Since data already exists in the serial port of the dual port memory 11, the serial interface 10 outputs the serial clock and data enable signals to read and store data from the serial port of the dual port memory 11. Since the read data is 16 bits, SC
The data is divided into 8 bits and transferred to the 3I controller 38. While reading out the pigs in this way, at the same time, the serial interface 1 reports how many have been read out.
0 is counting, and at the same time when all the data of the serial port of the dual port memory 11 is read, a read transfer cycle request is made to the memory controller 13 to transfer the data of the next address to the serial port. The memory controller 13 performs a read transfer cycle to the dual-bottom memory 11 by shifting it by the number of serial buffers.

If the range of one memory block is exceeded, a read transfer cycle is performed to the next memory block. Also, when writing data from scanner 1, first
I controller 3. Serial interface 10. Data flows to the dual port memory 11, but if nothing is done, it is not known whether writing to the first line buffer is in read mode or write mode, so a pseudo write transfer cycle is performed for each memory block before every write. The memory controller 13 performs this. This causes the write enable signal (WE signal) to go LOW at the falling edge of the row address strobe signal (RAS signal), the DT signal, and the S
Set the E signal to HIGH. In a normal write transfer cycle, the SE signal is set to LOW. In addition, in the read transfer cycle, the row address strobe signal (RAS signal) is LOW, and the write enable signal (WE signal) is LOW.
Set the OW and DT signals to LOW. In this way, data transfer is performed after the dual port memory 11 is ready,
The serial interface 10 counts that the serial port buffer is full and requests the memory controller 13 to perform a normal write transfer cycle.

The memory controller 13 performs a write transfer cycle,
After that, the address of the next write transfer cycle is determined, and if it exceeds the range of the memory block, the next memory block is enabled first. In this way, image pigs are read into a plurality of memory blocks.

Next, the operation of the image decompression device 15 shown in FIG. 1 will be explained.

One side of the memory controller 13 is the memory controller 1.
3, and the other end is connected to the bus width adjustment device 16.

The memory controller 13 has registers that determine the image pitch, number of main scans, number of sub-scans, left offset, transfer start address, and transfer direction.
Data is read and written sequentially word by word. Since the image is a bit image, unnecessary data may be generated at the left and right edges. Writing to the dual port memory 11 is performed by using the write per bit function to set the data bit to be masked to LOW when the RAS signal falls. The leftmost mask data is determined by the left offset register, while the rightmost mask data is synthesized from the left offset register and the main scanning number register. When the image reaches the right edge, it automatically moves to the left edge of the next line. In addition, it has two address systems for the dual port memory 11 for each 8-bit data, and when the transfer address is an odd number, the even number byte address has rIJ more than the odd number byte address. The data is also designed such that the odd and even bytes are reversed, so that even if the transfer start address or pitch is an odd number of bytes, one word of 16 bits of data can be transferred in one transfer. In this way, the image compression/expansion device 15 exchanges data with the memory controller 13, but the image compression/expansion device 15 contains registers for commands that determine the number of main scans, the number of sub-scans, the left offset number, compression or expansion, etc. be. In this way, the compressed data is passed to the bus width adjustment device 16, the 16-bit data is converted into 32-bit data, and the compressed data is transferred to the DRAM 31 through DMA processing by the memory controller 32 with a DMA controller. The developed image data is written into the photo memory 11. In addition, if a dual port memory 11 with an arithmetic function is used, the column address strobe signal (CAS signal) and WE signal will be LOW when the RAS signal falls.
If you set the calculation mode using the address line, you can perform AND, OR, EXCLUSIVE on the written data.
It is possible to perform arithmetic processing such as OR.

〔Effect of the invention〕

As explained above, the present invention restarts the bus cycle while temporarily suspending the output bus cycle when in the read modified write mode or when there is a response from the output bus and the read and write modes are manually switched. Since the bus cycle control means is provided, it is possible to reduce the burden on the memory controller when executing various bus cycles, and has excellent effects such as greatly simplifying bus access by the memory controller, which is a bus resource. play.

[Brief explanation of drawings]

FIG. 1 is a system block diagram illustrating the configuration of an information processing device showing an embodiment of the present invention, and FIG. 2 shows an example of inversion processing of the most significant bit of the address line of the sub CPU shown in FIG. 3(a) to (h) are detailed block diagrams explaining the configuration of the arbiter shown in FIG. 1, and FIG. 4 shows the peripheral circuit configuration of the arbiter shown in FIG. 5 and 6 are flowcharts illustrating an example of the sub-CPU start-up processing procedure shown in FIG. 1, and FIG. 7 is a block diagram illustrating the bus width adjustment device and DMA
110 device, FIG. 8 is a timing chart explaining the operation of FIGS. 3(a) to (h), and FIGS. 9(a) to (c) are diagrams illustrating the operation of FIGS. Flowcharts illustrating an example of cursor/window processing procedures for the information processing apparatus, FIGS. 10(a) and 10(b)
) is a flowchart explaining an example of the dragging processing procedure by the sub CPU and the main CPU in the information processing device according to the present invention, and FIGS. 3 is a flowchart illustrating an example of a pop-up menu display processing procedure. In the figure, 9 is a sub CPU, 13 is a memory controller, 1
4 is an arbiter, 16, 37.40 is a bus width adjustment device, 31 is a DRAM, 32 is a DMAC 133 is a main circuit.
PU and 3B are 5CSI interfaces. (a) Sub CPU cursor display process (b) Sub CPU communication interrupt (C) Main CPU window rewrite bus (a) Figure 0 (b)

Claims (1)

[Claims] A CPU and a direct memory access controller are connected to a system bus, and an arbiter arbitrates bus rights requests from the direct memory access controller and the CPU to the system bus, and the direct memory access controller directly communicates with each direct memory access device. In an information processing device that can perform memory access or access between each direct memory access device by the CPU, when there is a read modified write mode or a response from the output bus, and when the input bus switches between read and write modes, the output An information processing device comprising a bus cycle control means for restarting a bus cycle while temporarily suspending the bus cycle.