JPH03180955A - Information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) This invention relates to an information IA management device that executes data processing of each device while adjusting bus rights between a CPU connected to a system bus and a direct memory access controller. It is related to.

[Conventional technology]

Conventionally, when performing DMA control in this type of device, the data and address buses are shared between the cPU and the DMA transfer hardware, so it is necessary to adjust the bus ownership, which can be roughly divided into the following ( The transfer methods 1) and (2) are adopted.

(1) A method of performing transfer using the time when the CPU is not accessing the bus (cycle stealing method).

(2) A method in which the DMA III control circuit is a high-light circuit and transfers while stopping the CPU.

Of these, method (2) is further subdivided into a method in which control is returned to the CPU for each byte of transferred data (byte mode), a method in which control is returned to the CPU for each byte of transfer data, and a method in which DMA is used while a data request is received from an I10 device.
There are two types of methods: a method in which the control side continues to hold the right (continuous mode), and a method in which the DMA side holds the right until the transfer of the required number of bytes is completed (burst mode).

[Problem to be solved by the invention]

The arbiter circuit in conventional information processing devices is provided for each bus master, and bus access is executed by giving up bus master C bus rights according to various priorities. Since this requires a total of two clocks (one clock), there is a problem in that the efficiency of the arbitration process cannot be improved.

This invention was made to solve the above problems, and by coordinating adjacent bus requests from each bus master, it is possible to speed up single access by a bus master, and also safely execute adjacent accesses. The purpose is to obtain an information processing device that can perform the following steps.

[Means to solve the problem]

The information processing apparatus according to the present invention is provided with an adjusting means for switching and adjusting the bus right to each bus master while delaying for a predetermined time based on the proximity state of the generation of the bus right request from each bus master.

[Effect]

In this invention, when a bus request is generated from each bus master, the adjusting means switches and adjusts the bus right to each bus master with a predetermined time delay based on the proximity of the bus request from each bus master. This makes it possible to speed up individual access and safely perform close access.

(Embodiment) FIG. 1 is a system block diagram illustrating the configuration of an information processing apparatus showing an embodiment of the present invention. Reference numeral 1 denotes a scanner for inputting still images. 2 is a printer that outputs the print result. 3 is a 5csr controller that performs human output of data from the scanner 1 and printer 2. 4 is high definition type C
RT display, 6 is pointing device, 2
Use keys to specify coordinate information, icons, etc.

Reference numeral 7 denotes an interface (I/F) that processes coordinate information and the like from the pointing device 6. 8 is memory,
Stores program data of the sub CPU 9. An interface 10 inputs and outputs data on the serial port side of the dual port memory, and has a built-in timer for periodically referencing the state of the pointing device 6.

11 is a dual port memory for a scanner and printer having a random port and a serial port; 12 is the C
Dual port memory for RT display 4, 13 is memory controller tab, dual photo memory 11.12
refresh, serial read, serial write, pseudo write transfer timing, CPU access, and two-dimensional DMA. 14 is an arbiter (arbitrator), which is a sub-CP
U9.33. It controls the adjustment of the bus right of the DMA controller (DMAC) 13 and performs interrupt handshaking between the sub CPU 9 and the main CPU 33. 15 is an image compression/expansion device that compresses/expands image data. 16 is a device that inputs and outputs data by matching the compression code of the image compression/decompression device 15 to the bus width of the bus 44; A device 17 performs XY conversion on the image data.

A device 18 processes thinning and interpolation of image data. Buffers 19 to 21 drive the bus.

22 is FROM, which stores a boot program and interrupt vectors when the power is turned on. 23 is a static RAM used at startup, and 24 is a device that manages time and stores system management information even when the power is turned off. 25
is a counter that performs process switching and time measurement. 2
6 is an interrupt controller that outputs a vector when an interrupt occurs. 27 is an interface that supports serial communication. 2 is a modem connected to a public line, and 29 is an interface for inputting keys from a keyboard 30. 31 is dynamic RAM
(DRAM) stores program data on the system side. 32 is a memory controller with a DMA controller, which controls refresh of the DRAM 31 and DMA between the memory and each device. 33 is a main CPU, and 34 is a device which performs address decoding, interrupt control, and control of each control line. 35 is a board with built-in fonts of various typefaces and kana-kanji conversion dictionaries, etc. 36 is an interface, IEEE 802.3
+7) Supports 10BASE5 (so-called ETHRNET). 37 is a device constituting the bus width adjustment means according to the present invention, which interfaces the 8-bit human output SC3I controller 38 (constituting the direct memory access device) and the data bus 45 having a data width of 32 bits; A hard disk 41 with a 5C3II/F is an interface device that performs interfacing between the floppy disk controller and the bus 45. 42 is a 3.5-inch floppy disk drive, 43 is a bus with a 16-bit data width, and 44 is a 3.5-inch floppy disk drive.
．． 45 is a bus with a data width of 32 bits, and 46 is a bus with a data width of 32 bits.
A bus having a data width of 6 bits, 47 is the sub CP
This bus has a data width of 16 bits and can be accessed only from U9, and is configured so that the polarity of the most significant bit of this address line can be inverted with respect to the polarity of the address line coming out from sub CPU9. 40 is a bus width adjustment device.

In the information processing apparatus configured in this way, each bus master (in this embodiment, sub CPU 9, main CPU 33
．． When a bus request is generated from a bus request (DMACl3, etc.), an adjusting means (a flip-flop circuit to be described later) provided in the arbiter 14 delays the bus request to each bus master for a predetermined period of time based on the proximity of the bus request from each bus master. This allows for faster individual access by each bus master, as well as safer access for adjacent bus masters.

FIG. 2 is a circuit block diagram showing an example of polarity inversion processing of the most significant bit of the address line of the sub CPU 9 shown in FIG. Based on exclusive OR circuit (
The Q output is sent to EX-OR circuit) 101.

3(a) to 3(h) are detailed block diagrams illustrating the configuration of the Avita 14 shown in FIG. shows.

In these figures, 201 to 205 are EX-OR circuits, 206 is an inverter, 207 to 211 are EX-OR circuits, 212 is an inverter, 213.214 is a NAND circuit, 215 is an inverter, 216 is an AND circuit, and 217 is a NAND circuit, 218 is an AND circuit, 219 is a NAND
Circuit, 220 is an AND circuit, 221 to 223 are JK Philip flops (JKFF) with reset terminal, 224
is a NOR circuit, 225 is an inverter, 226.227 is a NOR circuit, 228 is an inverter, 229 to 232 are N
OR circuit, 233 is an OR circuit, 234 and 235 are D flip-flops (DFF), 236 and 237 are inverters, 23B is an OR circuit, 239 is a DF F,
240 J KFF, 241 is an inverter, 242 is a NAND circuit, 243 is an AND circuit, 244 is an inverter, 245 to 247 are DFFs, 248 is a NAND circuit,
249 is an AND circuit, and 250 is a JKFF.

251.252 is DFF, 253 is AND circuit, 254
is an inverter, and 255 to 257 are DFFs.

258 is a NAND circuit, 259 is an AND circuit, 260 is a JKFF, 261 and 262 are DFFs, 263.264 is a DFF, 265 to 267 are NAND circuits, 268 is an inverter, 269.270 is a NAND circuit, 271 is an inverter, 272° 273 is a NAND circuit, 274 is an inverter, 275.276 is a DFF, 277 to 279 are N
AND circuit, 280 is an inverter, 281.282 is A
ND circuit, 283 is a NOR circuit, 284 is a 3-state buffer, 285 is an inverter, 286 is a NOR circuit, 2
86 is a NOR circuit, 287 is an inverter, 288 is a NO
R circuit, 289 is an inverter, 290, 291 are NOR
circuit, 292 is a 3-state buffer, 293 is an inverter, 294 is a NOR circuit, 295 is an inverter, 296
is N.

R circuit, 297 is an inverter, 298 is a NOR circuit, 2
99 is an inverter, 300 is a NOR circuit, 301 is an inverter, 302 is a NOR circuit, 303 is a NOR circuit, 3
04 is a 3-state buffer, 305 and 306 are inverters, 307 to 310 are NOR circuits, 311 is an AND circuit, 312 and 313 are NOR circuits, 314 is a 3-state buffer, 315 to 326 are OR circuits, and 327 is an AND circuit , 328 is 5RFF, 329 is NAND circuit, 330
is an OR circuit, 331 is a NAND circuit, 332 is an OR circuit, 333, 334 is a NAND circuit, 335.336 is an A
The ND circuit, 337.338, is 5RFF.

FIG. 4 is a block diagram illustrating the peripheral circuit configuration of the arbiter 14 shown in FIG. It is a path transceiver.

Next, the start-up processing operation of the sub CPU 9 etc. shown in FIG. 1 will be described with reference to FIGS. 5 and 6.

FIGS. 5 and 6 are flowcharts illustrating an example of the procedure for starting up the sub CPU 9 shown in FIG. 1.

Note that (1) to (9) and (11) to (25) indicate each step.

When the power is turned on, the main CPU 33 first boots up, inputs the values of the stack pointer and program counter at the time of reset from the FROM 22, and performs startup processing.

At this time, the sub CPU 9 displays a cursor on the dual port RAM 11 based on the signal from the bonding device 6, controls the 5C3I controller 3, and controls the scanner 1. The steps include transferring image signals to the printer 2 and performing an interrupt handshake with the main CPU 33 via the arbiter 14.
), check the size that includes the entire program,
Set the number of words to transfer. Next, the transfer start address as seen from the main CPU 33 of the dual port memory 12 is set (2).

Next, data including programs and the like is transferred from the FROM 22 or DRAM 31 to the dual port memory 12 (3). Next, a data sum is performed to add the data value to a certain register or memory (4), and it is determined whether the transfer is completed, that is, whether the number of transfers remains is "0" (5), and N.

If so, return to step (3), and if YES, transfer the added data value (checksum) (6).

Next, the JSTART signal is given to the arbiter 14, and the sub CPU 9 to which the reset signal has been applied until now starts (7>).

Next, the sub CPU 9 inputs the stack pointer and program counter from the dual port memory 12, and executes the program loaded in the dual port memory 12 in static R according to the flow shown in FIG.
Load it into AM8, and invert the most significant bit of the address so that the interrupt vector of sub CPU9 is switched to static RAM (SRAM)8.

Next, it waits for an ACK interrupt to occur (8), and when the interrupt occurs, writes an interrupt response command JIQACK to the IBM register (9), ends the process, and moves on to the process by the sub CPU 9.

The size including the entire program is checked and the number of words to be transferred is set (11). Next, dual port memory 1
The transfer start address as seen from the main CPU 33 of No. 2 is set (12).

Next, data including programs and the like is transferred from the FROM 22 or DRAM 31 to the dual port memory 12 (13). Next, data sum is performed to add the data value to a certain register or memory (14), and it is determined whether the transfer is completed, that is, whether the number of transfers is rQJ remaining (15). If NO, step (13) is performed. ), if YES, determine whether the checksum is OK or not (16), if NO, proceed to step (23) and onwards, and Y
If ES, data is written to the inversion register (17
), determine whether the checksum of SRAM8 is OK (18), if NO, proceed to step (23) and onwards, and Y
If it is ES, write the normal status to the VRAM buffer (19) and send the interrupt command KIQA to the 18M register.
Write CK (20). Wait for the ACK interrupt to occur (21), and when the interrupt occurs, write the interrupt clear command KIQCLR to the 18M register (22)
), the process ends.

On the other hand, if No in steps (18) and (18), V
Write error status to RAM buffer (23)
, writes the interrupt command KIQACK to the 18M register (24). Wait for ACK interrupt to occur2
5) When an interrupt occurs, write an interrupt clear command KIQCLR to the 18M register (26) and end the process.

Specifically, the most significant bit of the address is input to one side of the EX-OR circuit 101 shown in FIG. 2, and the output of the flip-flop 102 is input to the other side.
By inverting the output of 2, the polarity of the most significant bit of the address is switched. Next, a message indicating that the program transfer has been completed is written to the communication buffer with the main CPU 33 provided in the dual port memory 12, and
Give the K I ACK signal to the arbiter 14, and
This is done by applying an interrupt signal to u33. Main CPU
33 receives the interrupt signal from the arbiter 14 and sends the JIAC
K is sent to the arbiter 14 to interrupt the sub CPU 9. The sub CPU 9 sends the KIQCLR signal to the arbiter 14 as an interrupt clear signal, and the initial operation of the sub CPU 9 ends.

Next, by transferring the bitmap data to the dual port memory 12, the bitmap image can be displayed on the CRT display 4 through the interface 5.

Next, the OS (operating system) and application program (AP) are transferred from the hard disk 39 to the dynamic RAM 31, or in this system, the DMA controller (DMAC) 32 and bus width adjustment device 37 are normally connected to the main CPU 33 and 8-bit width data transfer is being performed between
When outputted from the I controller 3B and input manually to the bus width adjustment device 37, the bus width adjustment device 37
When entering the MA transfer mode and writing data in the dynamic RAM 31 to the hard disk 39, the bus width adjustment device 37 outputs a DMA request to the DMA controller 32.

The DMA controller 32 requests bus ownership from the main CPU 33, and when the main CPU 33 releases the bus,
The DMA controller 32 takes control of the bus and writes 32-bit width data to the bus width adjustment device 37. The bus width adjustment device 37 cancels the DMA request, thereby also releasing the DMA controller 32 and the main CPU 33 taking control of the bus again.

On the other hand, the bus width adjustment device 37 decomposes 32-bit width data into 8-bit width data and writes the data to the SCSI controller 38 when a request is being output. When the four writes are completed, there is no data in the bus width adjustment device 37, so the bus width adjustment device 37 outputs a DMA request to the DMA controller 32 again and repeats the above operation. The SCSI controller 3rd transfers data to the pigeon disk 39 in accordance with the 5csr standard. A series of operations are performed until data of a fixed block length is transferred. The bus width adjustment device 37 receives a DMA transfer end signal from the DMA controller 32.

When a transfer end signal is generated from the NE or 5C3I controller 38, the DMA transfer mode is automatically terminated, and the normal mode is entered and the SC3I controller 38 and main C
The PU 33 can now communicate. Also,
Transfer data from hard disk 39 to dynamic RAM 31
When writing to C, write 5C3I to the lotus width adjustment device 37.
The only difference is that the bus width adjustment device 37 outputs a DMA request to the DMA controller 32 after writing the data of 3 days to the controller 4 times, and that the data transfer direction is reversed. The operation is similar to writing to a disk.

In this way, by providing the bus width adjustment device 37, even if there is a device in progress of DMA transfer, the main CPU 3
3 can execute a program by taking control of the bus between transfers without having the DMA controller 32 take control of the bus all the time.

However, the DMA10 device, in this example 5c
In the sr controller 38, a problem occurs when the read signal and the write signal are processed by a simple OR operation from the CPU and the bus width adjustment device 37. The read signal and write signal output from the bus width adjustment device 37 are D
Although only generated during MA, read signals and write signals output from the CPU are output for other Ilo's even during DMA when the CPU holds the bus right. Naturally, since the timing is different from that of the read signal and write signal generated from the bus width adjustment device 37, there is a possibility that the SCSI controller 38 malfunctions. To prevent this, there is a method of providing a signal indicating that DMA is in progress and switching the signal between the bus width adjustment device 37 and the CPU, and a method of switching the signal from the CPU to the SCS I controller 3B only when the CPU accesses the SCS I controller 3B (during chip selection). There is a method of inputting read/write signals, but the latter method is optimal in order to satisfy the tying.

FIG. 7 is a block diagram illustrating the connection relationship between the bus width adjustment device and the DMA110 device, where 401 is the bus width adjustment device, 402 is the DMA110 device, and 40
3.404 is an OR gate, and 405.406 is an AND gate.

DMA10 device 402 and bus width adjustment device 40
1 DMA transfer is performed using a REQ signal and an ACK signal. Normally, the CPU accesses the chip select signal, read signal, and write signal to the DMA10 device 402. It is input to both bus width adjustment devices 401, and DMA1
Reading and writing to the 0 device 402 is accessed using 8 bits. DMA command is issued and DMA10
When the REQ signal is output from the device 402, the bus width adjustment device 401 enters the DMA transfer mode, and performs 32-bit data transfer with the system bus. When the bus width adjustment device 401 receives the REQ signal, it returns an ACK signal, but at the same time, it changes the DMA RD signal or DMAWR signal to LOW level depending on the transfer direction, and sends the RDB signal to the DMA10 device 402 via AND gates 405 and 406. Send WRB signal. The CPU may issue read signals and write signals for each I10 if the system bus is not occupied by the DMAC, and the read signals and write signals are simply AND gated 405 and 401.
R and the RDB signal of the DMA10 device 402, WR
If the B signal is manually manipulated, DMA transfer may not be performed normally.

Therefore, the chip select signal, read signal, and write signal are ANDLed by OR gates 403 and 404, and then AN
If the D gates 405 and 406 are ORed, no malfunction will occur. Of course, each of these gates can also be built into the bus width adjustment device 37.

Also, the bus width adjustment device 40. The operations of the floppy disk controller 4i and the 3.5 inch floppy disk drive are substantially similar.

The DMA controller 32 has three sets of DMA channels, and parallel transfer between a hard disk and a floppy disk is also possible. Further, the operation of the arbiter 14, which controls the access of the main CPU 33 and the sub CPU 9 to the dual port memory 11.12 at the same time, will be explained with reference to FIG. 3(a).

EX-OR circuits 201 to 205 are used for address selection of the dual port memory 11.12 when viewed from the sub CPU 9, and EX-OR circuits 207 to 211 are used for main cp
Dual port memory 11.12 when viewed from u33
used for address selection. Unnecessary gates are connected so that the output is HIGH.

Boats KLVL1 to 5 of EX-OR circuits 201 to 205
and boat JLVL of EX-OR circuits 207 to 211
Input the level of polarity opposite to the polarity of the address to be selected into I~5, and input the level of polarity opposite to the polarity of the address to be selected, and
A bit is connected to 5 to determine the address to be selected. As a result, when the sub CPU 9 outputs the address of the dual port memory 11.12, the EX
The outputs of the OR circuits 201 to 205 all become HIGH, and the address strobe signal KASB becomes LOW, so the output of the inverter 206 becomes HIGH and the N
The output of the AND circuit 213 becomes LOW. As a result, N
The output of the OR circuit 217 becomes HIGH, and at the rising edge of the CLK signal, the Q output of the JKFF 222 becomes HIGH and the inverted Q output becomes LOW. The NOR circuit 217 also selects the memory controller 13 when the signal KLC5B is LOW.
The output will be HIGH even if it is. Similarly, the main CPU
When the addresses of the dual port memories 11 and 12 are output from 33, the outputs of EX-OR circuits 207 to 211 all become HIGH, and the address strobe signal J
Since ASB becomes LOW, the output of inverter 212 becomes HIGH, and the output of NAND circuit 219 becomes LOW. As a result, the output of the NAND circuit 219 becomes HIGH.
Then, at the rising edge of the CLK signal, the Q output of JKFF3 223) and the inverted Q output of IIGH1 go LOW. The NAND circuit 219 also outputs HIGH even when the signal JLC3B for selecting the memory controller 13 becomes LOW.

Furthermore, when the memory controller 13 sets the LBRB signal to LOW to perform DMA transfer, the inverter 21
5 or HIGH, and JKF at the rising edge of the CLK signal.
The Q output of F221 becomes HIGH1 and the inverted Q output becomes LOW. In this way, the inverted Q outputs S3. of JKFF221-223. If S6゜Sll becomes LOW at the same time,
Output S8 and output ■ of NOR circuit 227 and 232 are HIG
becomes H, and as a result, the output ■ of the NOR circuit 224 becomes LOW.
, the output (2) of the NOR circuit 229 becomes LOW.

In other words, only the output ■ becomes HIGH, and the output ■ becomes HIGH.

Output ■ becomes LOW. Similarly, output S3. S6 is LO
W, when output Sll is HIGH, only output output ■ is HIGH
The output becomes IGH, and the output ■ and the output ■ become LOW.

Similarly, output S3. Sll is LOW, output S6 is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW.

Similarly, output S6. Sit is LOW, output S3 is HIG
In the case of H, only output ■ becomes HIGH, and outputs ■ and output ■ become LOW. Also, when output S3 is LOW alone, when output S6 is LOW alone, only output ■ is LOW.
Therefore, when the output S11 is LOW alone, only the output (2) becomes LOW.

In other words, the arbiter 14 has a fixed priority order,
The output is defined as Sll>S6>53. In this way, when any one of the outputs ■, ■, ■ becomes HIGH, the output S14 of the OR circuit 233 also becomes HIGH, and the inverter 236 outputs the signal at the falling edge of the CLK signal.
FF234 latches output S14 and output S becomes Q output
15 becomes HIGH. The inverted Q output is LOW, and since it is connected to the inverted S input of the DFF235,
S16, which is the inverted Q output of DFF235, immediately goes LOW.
becomes. As a result, the output S7 of the NOR circuit 226 becomes the same level as the output ■, and if the output ■ is HIGH, the output S7 is also HIGH, and the output S6 is LOW.
Even if it becomes N.

The output S8 of the R circuit 227 is prevented from becoming HIGH. In other words, the output ■ becomes HIGH and the DFF235
When the inverted Q output S16 of becomes LOW, the output S6 becomes LOW.
Even if the voltage becomes W, the NOR circuit 224 does not cause the output ■ to go LOW. This allows stable access. Similarly, the output S13 of the NOR circuit 231 is set to HIGH by the NOR circuit 230 when either the output ■ or the output ■ is HIGH, so that the output ■ of the NOR circuit 232 does not become HIGH even if the output Sll becomes LOW. become. In other words, output ■ and output ■ become HIGH and become 0.
When the output S16, which is the inverted Q output of the FF 235, becomes LOW, even if the output Stt becomes LOW, the NOR circuit 224
, 229, the outputs ■ and ■ are never set to LOW. In this way, once a lower priority run cycle is started, it cannot be interrupted by higher priority inputs until the run cycle is finished. JKFF223
The output S11, which is the inverted Q output, is LOW and the output ■ is HI.
Output S1 becomes GH and becomes the inverted Q output of DFF235.
6 becomes LOW and the execution cycle begins, as shown in Figure 3 (
The LJB output also becomes LOW due to the inverter 254 in b). The LJB output includes the tri-state input of the address buffer 352 of the main CPU 33 and the data buffer 35.
The main CPU 33 is connected to the tri-state input of the bus 43, thereby giving bus authority to the main CPU 33.

The memory controller 13 accesses the dual port memory 11.12 according to the address and returns a data acknowledge signal LDTKB to the arbiter 14. In the arbiter 14, the inverter 271. shown in FIG. 3(C). It is output as a JDTAK signal through a NAND circuit 269270. This signal is returned to the main CPU 33, and the main CPU
33 sets the JASB signal to HIGH and the cycle ends. As a result, the output SIO of the AND circuit 220 in FIG. 3(a) becomes HIGH, and the output SIO of the NOR circuit 238 becomes HIGH.
17 becomes LOW, and the Q output sis of DFF234 becomes LOW.
OW, inversion Q becomes HIGH.

Here, when the CLK signal goes from LOW to HIGH, J
Output S11, which is the inverted Q output of KFF223, is HIGH
Therefore, the output ■ of the NOR circuit 232 is LOW, as shown in Fig. 3 (
The output LJAS of the AND circuit 259 shown in b) also becomes LOW, and the bus right of the image bus is released from the main CPU 33. At the rising edge of the CLK signal, JKFF223
At the same time, the output S16, which is the inverted Q output of the DFF 235, also becomes HIGH, and the output S3. S6. The adjustment cycle for each Sll signal begins.

Here, output S6 only or output S3. If S6 is LOW, the sub CPU 9 takes control of the bus as described above, and the data acknowledge signal LDTKB of the memory controller 13 is activated.
similarly ends the bus cycle.

On the other hand, in the arbiter 14, the DFF 25 shown in FIG.
There is 1,252,261.262, main cpU33
If the accesses of the sub CPU 9 and the sub CPU 9 are close to each other, the L
In order to prevent the ASB signal and LDTKB signal from affecting the memory controller 13 and each CPU 9.33 due to delay time, etc., the LJ is
The AS signal and LKAS signal are separated so that they do not come close to each other. Even if the output ■ becomes LOW and immediately the output ■ becomes HIGH, the Q output of the DFF 261 becomes LOW, the inverted Q output of the DFF 262 begins to become HIGH, and the LKAS signal becomes HIGH. The same applies to the LJAS signal. In addition, the LASB shown in FIGS. 3(d) to (f)
signal, LUDSB signal, LLDSB signal, LRW signal,
Each signal of LC3B signal and JDT shown in Fig. 3(c)
The AK signal, KDTAK signal, JBER signal, and KBER signal are all valid unless either the LJAS signal or the LKAS signal is set to IGH. Access can be performed quickly and safely at short distances.

By the way, the JKFF221 is activated by the bus request signal LBRB from the DMA controller 13 on the image bus.
When the output s3, which is the inverted Q output, becomes LOW and the output ■ becomes HIGH, the JD
TAK signal, KDTAK signal, JBER signal, KBER
All of the signals become valid unless either the LJAS signal or the LKAS signal is HIGH. Thereby, individual access between the main CPU 33 and sub CPU 9 can be performed at high speed, or close access can be performed safely.

By the way, the LBRB signal, which is a bus right request, from the DMA controller 13 on the image bus causes the JKFF
Output S3, which is the inverted Q output of 1, becomes LOW and output ■
When becomes HIGH, as shown in Figure 3(b),
The inverted Q output of the DFF 239 becomes HIGH at the rising edge of the CLK signal, and the LB becomes the output of the NAND circuit 242.
GB signal becomes LOW. This indicates that the bus right has passed to the DMA controller 13, and the DMA controller 13 sets the LBGAKB signal to LOW and the LBRB signal to HIGH. As a result, the output of inverter 241 becomes HIGH, and the Q output of JKFF240 becomes LO.
It becomes W. As a result, the LBGB signal becomes HIGH. The DMA controller 13 starts data transfer and holds the LBGAK signal LOW until the data transfer is completed. When the data transfer is completed and the LBGAK signal is set to HIGH, the output S2 of the AND circuit 216 shown in FIG. 3(a) becomes HIGH, and the output S17 of the NOR circuit 23B becomes HIGH.
becomes LOW, and the output S1 becomes the Q output of the DFF234.
5 is set to LOW.

At the rising edge of the CLK signal, output S3, which is the inverted Q output of JKFF221, becomes HIGH, and at the same time, DFF235
The output 31B, which is the inverted Q output, also becomes HIGH, and the output (2) becomes LOW, entering the abitration cycle again. Access to the main CPU 33 is indicated by the JASB signal being LOW in a normal cycle, but in order to synchronize the software of the main CPU 33 and sub CPU 9, a read and write cycle that must not be divided, a so-called read-modify-write cycle, is performed. be.

At this time, the main CPU 33 recognizes that this cycle is occurring by turning JRM CB (No. 3 LOW).

This JRMCB signal is manually input to the AND gate shown in Figure 3(a), and the JASB signal becomes HIGH.
In a normal cycle, the output 10 becomes HIGH to end the cycle, but when the JRMCB signal is LOW, the cycle is not ended to support the read-modify-write cycle. On the other hand, sub CPU
The 9 side does not have a KKRMCB signal and supports the following processing.

The KRW signal is HIGH1, that is, KA in the read cycle.
The SB signal becomes LOW, then the KUDSB signal or KLDSB signal becomes LOW, the dual port memory 11 or the dual port memory 12 is read, the memory controller 13 sets the LDTAKB signal to LOW,
The arbiter 14 outputs the KDTAK signal.

This causes the KUDSB signal or KLDSB signal to go high.
IGH, the KRW signal goes LOW while the KASB signal remains LOW, and the KUDSB signal or KLDS goes LOW again.
B becomes HIGH and data is written to the dual port memory 11 or the dual port memory 12. The memory controller 13 again sets the LDTAKB signal to LOW. As a result, the KUDSB signal or KLDSB signal including the KASB signal becomes HIGH, and the cycle ends.

On the other hand, the memory controller 13 transfers all cycles to LA.
The period when the SB signal is LOW, the memory controller 13
It does not itself support read-modify-write cycles. For this reason, 0FF245-247. JKF
F250. LDTAK once by NAND circuit 248
The B signal goes LOW, and the KRW signal goes from HIGH to LOW.
When switched to W, the LKAS signal is set to LOW once, that is, the LASB signal is set to HIGH once.

When the LDTAKB signal becomes LOW, the inverter output LDT of the inverter 271 shown in FIG. 3(e) becomes HIGH.
becomes H, and the Q output of JKFF250 becomes HIGH.

When KRW goes from HIG) to LOW, DFF246
．． When the Q output of 247 is HIGH, the inverted Q of DFF245
Since the output is HIGH, during the two rises of the CLK signal, the LKAS signal is LOW and the LASB signal is HI.
It becomes GH. In this way, the arbiter 14 uses 2fi! ! It supports read-modify-write cycles of the same type, and does not change the image bus rights during this process. Further, the LASB signal always becomes LOW twice.

The arbiter 14 also supports interrupt handshaking between the main CPU 33 and sub CPU 9, and
3 is shown in FIG. 3(C) when the signal JD1 shown in FIG. 3(g) is set to LOW and the signals JRW and JC3B are set to LOW. , = D F F 263.264 and the NAND circuit 265 cause the JJB signal to go LOW between the rising edge of the CLK signal and the next rising edge, and the OR circuit 321.315 in FIG. 3(g) causes the JIQACK signal to go LOW.
It becomes W. As a result, the output of the OR circuit 330 becomes LOW, the output of the NAND circuit 331 becomes HIGH, and the output of the NAND circuit 331 becomes HIGH.
The KINTB signal, which is the output of the AND circuit 329, is LOW.
This signal becomes an interrupt signal to the sub CPU 9. The sub CPU 9 sets the KDI signal shown in FIG. 3(g) to L.
When the KRW signal and the KC3B signal are LOW as OW, the DFF275.276 and NA shown in Fig. 3(C) are
The ND circuit 279 makes the KKB signal LOW from one rise of the CLK signal to the next rise, and the third
KIQAC
The K signal becomes LOW. As a result, the output of the OR circuit 332 becomes LOW, and the output of the NAND circuit 333 becomes HIGH.
JINTB becomes H and becomes the output of the NAND circuit 334.
The signal becomes LOW, and this JINTB signal becomes the main CP
It becomes an interrupt signal to U33, and at the same time the NAND circuit 32
Return the KINTBip number, which is the output of 9, to HIG) (
Clear the interrupt signal. To clear only your own interrupt signal without interrupting the other party's CPU, clear the main CPU
PU33 turns the JD2 signal LOW instead of the JDI signal,
Sub cpu9 uses KD2 signal LO instead of KDI signal
If it deviates from W, the JIQCLR signal and KIQCLR signal become L.
It becomes OW and clears the interrupt. Also, the signal JD3. Set signal KD3 to LOW, JRW signal, JC5B signal to LOW, KPW signal, K
When the CSB signal is LOW, the JMSKST signal and KM
SKST signal becomes LOW, 5RFF328.337
The Q output of becomes I(IGH, and the OR circuit 330.332
The output will no longer go LOW, and no interrupt signal will be generated. The interrupt can also be canceled by setting the JD4 signal and KD4 signal to LOW, the JRW signal and JC3B signal to LOW, and the KRW signal and KCC3B signal to LOW. Also, if the JD5 signal, JRW signal, and JC3B signal are LOW from the main CPU33, then the KR
The ESB signal can be made HIGH, and this can be
If it is used as a reset signal for the PU 9, the sub CPU 9 can be started from the main CPU 33. JD6 signal, J
By setting the RW signal and the JC3B signal to LOW (see FIG. 8), the sub CPtJ9 can be reset again.

The data transfer process will be specifically explained below, taking as an example a case where a window and a cursor are displayed on the CRT display 4 using the dual port memory 12.

Not all areas of the dual port memory 12 are used for display, and some areas can be used as completely free RAM. This dual port memory 12
Since it can be accessed from both the main CPU 33 and the sub CPU 9, it is most suitable as a communication buffer. An arbiter 14 is used to interrupt the other party, and the state of the command or response at that time is exchanged in the communication buffer in the free area of the dual port memory 12.

In this system, the sub CPU 9 displays the cursor, and the main CPU 33 creates windows and rewrites the contents of the windows. Therefore, main C
When the PU 33 uses VR and AM, it writes a window rewriting request command and window coordinates in the communication buffer, issues a J I QACK signal command to the arbiter 14, and interrupts the sub CPI J9. Sub CPL
19 receives the window rewrite request command from the communication buffer using the KINTB signal, which is an interrupt signal, and turns on the busy flag. Next, the coordinates of the four corners of the window are taken, and a clipping operation is performed on the window where the cursor is displayed. As a result, the cursor and main CPU 33
If there is an overlap between the windows that are being rewritten, the sub CPU 9 erases the cursor and restores the original image to that area. Then, KI for arbiter 14
It issues a QACK signal and causes the main CPU 33 to generate a JINTB signal as an interrupt signal. Main cpu33
rewrites the window in response to an interruption in response to this window rewrite command. If there is no overlap between the cursor and the window, do not erase the cursor and use KIQA.
Issue a CK signal. When the main CPU 33 finishes the window rewriting, it issues a JIQACK signal to the arbiter 14 in response to the complete rewriting command in the communication buffer, and causes the sub CPU 9 to generate a KINTB signal as an interrupt signal.

The sub CPU 9 thereby turns off the busy flag and issues a KIQACK signal to the arbiter 14, and the main CPU receives the generated JINTB signal interruption as a response to the termination command. The sub CPU 9 not only processes interrupts, but also positions the cursor in a separate routine, reads the coordinates of the pointing device every time a timer interrupt occurs in the interface 10, and if there is a difference from the previous one, saves the coordinates. Look at the busy flag that turns 0N10FF in the previous interrupt routine, and if it is ON, clip the rewrite window with the cursor window, if there is an overlap, do not display the cursor, and if there is no overlap and the busy flag is OFF, display the cursor. . Cursor display means to save the image in the cursor window, display a cursor such as an arrow, and when moving the cursor to another location, return the saved image, and then save the image again at the position you want to move. conduct.

Next, the cursor/window processing operation in the information IA management device according to the present invention will be explained with reference to FIGS. 9(a) to 9(C).

FIGS. 9A to 9C are flowcharts illustrating an example of a cursor/win control procedure in the information processing apparatus according to the present invention. In addition, (1) to (9), (1
11 to (19) and (21) to (26) indicate each step. Hereinafter, the process will be explained sequentially starting from the process shown in FIG.

When the timer interrupt processing occurs, the sub CPU 9 (1)
Read the coordinate values from the pointing device 6 (2
), determine whether there is a difference from the previous coordinate values 3)
, if No, return to step (1), and if YES, save the current coordinate values (4).

Next, determine whether the busy flag is ON or not 5).
If No, the process proceeds to step (9) onwards, and if Yes, the receiver takes the coordinates of the four corners of the rewriting window (6). Then,
Try clipping in the cursor window 7), judge whether there is overlap 8), and if YES, step (
Return to step 1), and if No, display the cursor 9) and return to step (1).

On the other hand, the communication interrupt process determines whether a window rewrite request has occurred, as shown in FIG.
12), Take the coordinates of the four corners of the rewrite window (13)
). Next, use the cursor window to select clipping mode 14
), it is determined whether there is an overlap (15), and if No, the process proceeds to step (17) and subsequent steps; if YES, the cursor is erased (6), a response command is issued (17), and the process ends.

On the other hand, if the determination in step (11) is NO, the busy flag is turned off (18), a response command is issued (19), and the process is terminated.

On the other hand, the main CPU 33 sends the coordinates of the four corners of the rewrite window to the communication buffer (21
), issue a window rewrite request command 22), wait for a command response from the sub CPU 9, etc. 23), and when a response is received, rewrite the window (2
4) Issue a command to end window rewriting (
25). Next, the process waits for a command response from the sub CPU 9 or the like (26), and ends the process.

Next, while referring to FIGS. 10(a) and (b), the sub-CP
The dragging process by the IJ9 and main CPU 33 will be explained.

FIGS. 10(a) and 10(b) are flowcharts illustrating an example of a dragging process procedure performed by the sub CPU 9 and the main CPU 33 in the information processing apparatus according to the present invention.

Note that (1) to (18) and (21) to (29) indicate each step.

The sub CPU 9 sends the cursor position to the communication buffer (
1) Issue an interrupt indicating that the left key is ON 2) Wait for a command response (3).

Next, it is determined whether it is a dragging command or command (4),
If No, perform another process, if Yes, take the window frame size position (5) and turn off the arrow cursor (6)
), the window frame is displayed in reverse (7). Next, wait for a timer interrupt to occur (8), and when the interrupt occurs, read the coordinate values of the pointing device 6 (9)
, to determine whether there is a difference from the previous coordinate values 10),
If No, return to step (8>); if Yes, save the coordinates (11), change the window frame position (12)
. Next, display the window frame (13), determine whether the key is in the OFF state (14), and if No, proceed to step (8).
), and if YES, transfer the window frame size position15) and issue an interrupt indicating that the left key is OFF16)
, waits for a command response to occur (17).Then, a command response is issued (18), and the process ends.

On the other hand, as shown in FIG. 10(b), when an interrupt is issued in step (2) above, the main CPU 33 checks the window at the cursor position (21), determines whether it is a dragging area or not (22), and The frame size, position, etc. are sent to the communication buffer (23), and a dragging command is issued (24). Next, it is determined whether there is a command response (25), and if YES, the window frame size and position are taken (26).

Next, the window is rewritten (27) and a window rewriting end command is issued (28). Next, it waits for a command response (29), and when the command response is issued, the process ends.

Next, the pop-up menu display processing operation of the information processing apparatus according to the present invention will be explained with reference to FIGS. 11(a) and 11(b).

FIGS. 11(a) and 11(b) are flowcharts illustrating an example of a pop-up menu display processing procedure performed by the information processing apparatus according to the present invention.

Note that (1) to (29) and (31) to (48) indicate each stem.

First, the sub CPU 9 sends the cursor position to the communication buffer (1) and issues an interrupt indicating that the right key is ON (2).
. Then, wait for a command response 3),
If YES, it is determined whether it is a pop-up menu command (4), if YES, the pop-up window row is read out (5), and the arrow cursor is turned off (6). Next, issue a response command 7) and wait for a command response 8). If YES, turn on the arrow cursor.
1/ (9), Please judge whether the right key is OFF or not 10
), if YES, proceed to step (24) and later, turn off the arrow cursor, and judge whether it is the selection area or not.
5) If YES, press the right key to 0FFL and issue an execution interrupt (26). Next, wait for a command response (28), and if YES, move the arrow cursor to 0NL (
29), the process ends.

On the other hand, if the determination in step (25) is No, the right key is turned OFF, a non-execution interrupt is issued (27), and the process proceeds to step (28).

On the other hand, if the judgment in step (lO) is NO, wait for a timer interrupt (11), and if YES, read the pointing device coordinate value (12) and judge whether there is a difference from the previous coordinate value. 13), if No, return to step (10); if YES, save the coordinate values 14), and display the cursor (15).

Next, determine whether it is a select area 16), YE
If S, proceed to step (19) and later; if NO, determine whether it is a subwindow creation area (17); if No, return to step (10); if YES, insert the subwindow (18), and step (17). Return to 3).

On the other hand, if the judgment in step (lli) is YES, judge whether it is a separate menu or not (19), if No, return to step (10), and if YES, turn the arrow cursor OFF.
(20), issue a select change interrupt (21),
Wait for a command response 22), and if YES, turn the arrow cursor ON L/ (23) and return to step (10).

On the other hand, as shown in FIG. 11(b), the main CPU 33 checks the window at the cursor position (31) and determines whether there is a window (32). If NO, it executes another process and displays the pop window row. 33) If YES, issue the pop-up menu command 134)
, waits for a command response (35). If YES, a pop-up window is created (36) and pop-up menu command 2 is issued (37). Next, wait for a select change interrupt (38), if No, proceed to step (41) and after, if YES, execute color change (39), issue a response command (40), and return to step (38). .

On the other hand, if the judgment in step (38) is No, it is necessary to judge whether a subwindow interrupt has occurred (41), YE.
If S, return to step (33); if No, right key O
Please judge whether it is an execution interrupt indicating FF42), YE
If S, delete the pop-up window44), issue a response command45), and execute the command46)
, ends the process.

However, if the judgment in step (42) is No, press the right key O.
43〉, N
If o, proceed to another process; if YES, delete the pop-up window47) and issue a response command48
), the process ends.

Next, 5C3I controller 3 and dual bottom memory 1
The processing operation of the serial interface 10 will be explained.

The dual port memory 11 is connected to the printer 2. Because it is used for one scanner, its capacity is much larger than the dual port memory 12 for CRT display 4, and when outputting one A4 size sheet at a pixel size of 400 dots per inch, it requires approximately 2M bytes. Capacity is required. Therefore, at present, 16 dual port memories using 1M bit chips are required. 256
If the bus width is 16 bits with a byte x 4 configuration, it will consist of four memory blocks that cannot be accessed simultaneously. Therefore, six memory blocks are required for B4 size and eight memory blocks for A3 size. When outputting to a printer, the 5csr controller 3 first requests data to the serial interface 10. Since there is no data yet, the serial interface 10 requests the memory controller 13 to perform a read transfer cycle. The memory controller 13 performs read transfer cycles during memory refresh, CPU access, etc., and returns response signals to the serial interface 10.

Since data already exists on the serial port of dual port memory 11, serial interface 1o
outputs serial clock and data enable signals,
Data is read from the serial port of the dual port memory 11 and stored. Since the read data is 16 bits, the data is divided into 8 bits and transferred to the 5CSI controller 38. As the data is read out in this way, the serial interface 10 counts how many data have been read out, and at the same time it reads out all the data on the serial port of the dual port memory 11, it sends the data at the next address to the memory controller 13. A read transfer cycle request is made to transfer the data to the serial port. The memory controller 13 shifts the dual port memory 1 by the number of serial buffers.
A read transfer cycle is performed for 1.

If the range of one memory block is exceeded, a read transfer cycle is performed for the next nine memory blocks. Also, when writing data from scanner 1, first,
5C3I controller 3. Serial interface 10
Data flows to the dual port memory 11, but if nothing is done, it is not known whether writing to the first line buffer is in read mode or write mode, so a pseudo write transfer cycle is performed for each memory block before every write. The memory controller 13 performs this. This is done by setting the write enable signal (WE signal) to LOW and the DT double signal SE signal to HIGH at the fall of the row address strobe signal (RAS signal). In a normal write transfer cycle, the SE signal is set to LOW. Also, in the read transfer cycle, the row address strobe signal (R
AS signal) is set to LOW, the write enable signal (WE signal) is set to LOW, and the DT double signal is set to LOW. In this way, data transfer is performed after the dual port memory 11 is ready, and the serial buffer 10 counts when the serial port buffer is full and requests a normal write transfer cycle from the memory controller 13. . The memory controller 13 performs a write transfer cycle, then determines the address of the next write transfer cycle, and if it exceeds the range of a memory block, enables the next memory block first. In this way, image pigs are read into a plurality of memory blocks.

Next, the operation of the image compression/expansion device 15 shown in FIG. 1 will be explained.

One side of the memory controller 13 is the memory controller 1.
3, and the other end is connected to the bus width adjustment device 16.

The memory controller 13 has registers that determine the image pitch, number of main scans, number of sub-scans, left offset, transfer start address, and transfer direction.
Data is read and written sequentially word by word. Since the image is a bit image, unnecessary data may be generated at the left and right edges. Writing to the dual port memory 11 is performed by using the sleep bar bit function to set the data bit to be masked to LOW when the RAS signal falls. The leftmost mask data is determined by the left offset register, while the rightmost mask data is synthesized from the left offset register and the main scanning number register. When the image reaches the right edge, it automatically moves to the left edge of the next line. In addition, there are two address systems for the dual port memory 11 for each 8-bit data, and when the transfer address is an odd number, the address of an even number byte is "1" more than the address of an odd number byte. At this time, the odd and even bytes of the data are inverted, so that even if the transfer start address or pitch is an odd number of bytes, one word of 16 bits of data can be transferred in one transfer. In this way, the image compression/expansion device 15 exchanges data with the memory controller 13, and the image compression/expansion device 15 includes registers for commands that determine the number of main scans, the number of sub-scans, the left offset number, compression or expansion, etc. . In this way, the compressed data is passed to the bus width adjustment device 16, and the 16-bit data is converted into 32-bit data and is transferred to the DRAM 3 by the DMAIA process of the memory controller 32 with the DMA controller.
The compressed image data is transferred to i, and in the case of expansion, the expanded image data is written in the dual port memory 11 in the opposite direction. In addition, if you use a dual port memory 11 with an arithmetic function, you can set the column address strobe signal (CAS signal) and WE positive signal LOW at the falling edge of the RAS signal, and set the arithmetic mode on the address line, and the data will be written. AND, OR, EXCLUS for the data
It is possible to perform arithmetic processing such as rVEOR.

〔Effect of the invention〕

As explained above, the present invention provides an adjustment means for switching and adjusting the bus right to each bus master while delaying for a predetermined time based on the proximity of bus request generation from each bus master. In addition to speeding up the speed, close access can be performed safely. Therefore, an excellent effect is achieved in which the efficiency of memory access processing by a plurality of bus masters can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a system block diagram illustrating the configuration of an information processing device showing an embodiment of the present invention, and FIG. 2 shows an example of inversion processing of the most significant bit of the address line of the sub-CPLI shown in FIG. Circuit block diagram shown in Fig. 3 (a) to (h)
is a detailed block diagram explaining the configuration of the arbiter shown in FIG. 1, FIG. 4 is a block diagram explaining the peripheral circuit configuration of the arbiter shown in FIG. 1, and FIGS. A flowchart illustrating an example of the sub-CPU startup processing procedure shown in Figure 1, and Figure 7 shows the bus width adjustment device and DM.
A block diagram explaining the connection relationship with the Al10 device,
FIG. 8 is a timing chart explaining the operations in FIGS. 3(a) to (h), and FIGS. 9(a) to (C) are examples of cursor/window processing procedures in the information processing apparatus according to the present invention. Flowchart to explain, FIGS. 10(a) and (b)
) 4 is a flowchart illustrating an example of the dragging processing procedure by the sub CPU and the main CPU in the information processing apparatus according to the present invention, and FIGS. 11(a) and 11(b) are pop-up menu displays in the information processing apparatus according to the present invention. It is a flowchart explaining an example of a processing procedure. In the figure, 9 is a sub CPU, 13 is a memory controller, 1
4 is the arbiter, 16 37.40 is the bus width adjustment device, 31 is the DRAM, 32 is the DMAC 133 is the main cp
u13B is the SCS I interface. (a) Figure (b) One step (C) Main CPU window Rewriting process (a) Figure 0 (b)

Claims (1)

[Claims] A CPU and a direct memory access controller are connected to a system bus, and an arbiter arbitrates bus rights requests from the direct memory access controller and the CPU to the system bus, and the direct memory access controller directly communicates with each direct memory access device. In an information processing device that can perform memory access or access between each direct memory access device by a CPU, switching and adjusting the bus right to each bus master with a predetermined time delay based on the proximity of the occurrence of a bus right request from each bus master. An information processing device characterized by comprising an adjusting means for adjusting.