JPH03181149A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03181149A JPH03181149A JP32180389A JP32180389A JPH03181149A JP H03181149 A JPH03181149 A JP H03181149A JP 32180389 A JP32180389 A JP 32180389A JP 32180389 A JP32180389 A JP 32180389A JP H03181149 A JPH03181149 A JP H03181149A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はスタンダードセル方式、又はセルベース方式の
半導体集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a standard cell type or cell-based type semiconductor integrated circuit device.
第3図は従来のセルベース方式の半導体集積回路装置を
示す模式的平面図、第4図は第3図に示す半導体集積回
路装置におけるB部分の拡大平面図であり、図中1は半
導体チップ、2は所定のまとまりのある機能ブロックを
1個の単位セルとするモジュールセルを示している。半
導体チップ1に;よそのアクティブエリア内に1箇又は
複数筒(図面には1箇のみ示す)のモジュールセル2が
、また周縁部には接地用のポンディングパッド3a、電
源用のポンディングパッド3b、信
ンディングバンド30等が設けられており、例えばモジ
ュールセル2の接地配線14に連なる接地端子14aと
接地用のポンディングパッド3aとの間、モジュールセ
ル2の電源電線15に連なる電源端子15aと電源用の
ポンディングパッド3bとの間は夫々配線17. 18
にて接続されている。FIG. 3 is a schematic plan view showing a conventional cell-based semiconductor integrated circuit device, and FIG. 4 is an enlarged plan view of part B in the semiconductor integrated circuit device shown in FIG. 3, where 1 is a semiconductor chip. , 2 indicates a module cell in which one unit cell is a predetermined group of functional blocks. On the semiconductor chip 1; one or more module cells 2 (only one is shown in the drawing) in the active area, and a grounding pad 3a and a power supply pad on the periphery. 3b, a transmission band 30, etc. are provided, for example, between the grounding terminal 14a connected to the grounding wire 14 of the module cell 2 and the grounding pad 3a, and the power terminal 15a connected to the power supply wire 15 of the module cell 2. Wires 17. and the power supply bonding pads 3b are connected to each other. 18
It is connected at.
ところで上述した如き、従来装置にあってはモジュール
セル2の接地配線14に連なる接地端子14a、電源配
線15に連なる電源端子15aはモジュールセル2の一
隅部に夫々各l箇のみしか設けられていないため、チッ
プ全体のフロアプラニングにおいて接地用のポンディン
グパッド3a、電源用のポンディングパッド3bとモジ
ュールセル2の接地端子14a,電源端子15a迄の配
線に対する自由度が小さく、配線17. 18の距離が
長くなり、これらのインピーダンス増大による特性劣化
を招く等の問題があった。By the way, in the conventional device as described above, only one ground terminal 14a connected to the ground wiring 14 of the module cell 2 and one power terminal 15a connected to the power supply wiring 15 are each provided in one corner of the module cell 2. Therefore, in the floor planning of the entire chip, there is little freedom in wiring between the grounding pad 3a, the power supplying pad 3b, and the grounding terminal 14a and power supply terminal 15a of the module cell 2, and the wiring 17. 18 becomes long, which causes problems such as deterioration of characteristics due to increased impedance.
本発明はかかる事情に鑑みなされたものであって、その
目的とするところはチップ全体のフロアプラニングにお
いて接地配線、電源配線に対する自由度を高め、電源配
線、接地配線の短縮を可能とする半導体集積回路装置を
提供するにある。The present invention has been made in view of the above circumstances, and its purpose is to increase the degree of freedom regarding ground wiring and power wiring in the floor planning of the entire chip, and to provide a semiconductor integrated circuit that can shorten the power wiring and ground wiring. To provide circuit equipment.
本発明に係る半導体集積回路装置は、モジュールセルに
接地端子、電源端子を夫々各複数個設ける。In the semiconductor integrated circuit device according to the present invention, a module cell is provided with a plurality of ground terminals and a plurality of power supply terminals.
本発明にあってはこれによって、各ポンディングパッド
と、モジュールセルの接地端子、電源端子とを接続する
配線のフロアプラニングにおける自由度が大きくなり配
線距離の短縮が可能となる。According to the present invention, this increases the degree of freedom in floor planning of the wiring connecting each bonding pad to the ground terminal and power supply terminal of the module cell, making it possible to shorten the wiring distance.
〔実施例〕
以下本発明をその実施例を示す図面に基づき具体的に説
明する。[Example] The present invention will be specifically described below based on drawings showing examples thereof.
第1図は本発明に係る半導体集積回路装置の模式図、第
2図は第1図のA 6N域部分の拡大平面図であり、図
中1は半導体チップ、2はモジュールセルを示している
。半導体チップ1にはそのアクティブエリア内に1箇又
は複数筒のモジュールセル2が、また周縁部には接地用
のポンディングパッド3a、電源用のポンディングパッ
ド3b、信号入力用のポンディングパッド30等多数の
ポンディングパッドが設けられている。一方モジュール
セル2の4隅には例えば第2図に示す如き態様でモジュ
ールセル2内部の接地配線4、及び電源配線5゜6に接
続される各2箇の接地端子4a、 4b、電源端子6a
、 6bが設けられている。接地配線4は半導体チップ
1の隅角部に導かれ、半導体チップにおける隅角部の2
辺辺縁に沿わせた態様で接地端子4a。FIG. 1 is a schematic diagram of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is an enlarged plan view of the A6N area in FIG. 1. In the figure, 1 indicates a semiconductor chip, and 2 indicates a module cell. . The semiconductor chip 1 has one or more module cells 2 in its active area, and has a grounding pad 3a, a power supply pad 3b, and a signal input pad 30 on its periphery. A large number of bonding pads are provided. On the other hand, at the four corners of the module cell 2, there are two ground terminals 4a, 4b and a power terminal 6a each connected to the ground wiring 4 and power supply wiring 5.6 inside the module cell 2, as shown in FIG. 2, for example.
, 6b are provided. The ground wiring 4 is led to a corner of the semiconductor chip 1, and is connected to two corners of the semiconductor chip.
Ground terminal 4a along the edge.
4bが設けられている。4b is provided.
一方電源配線5は半導体チップlの隅角部近傍において
スルーホール5aによって電源配線6に接続されている
。電源配線6は平面視でL形に形成されて7おり、その
両端部を夫々、半導体チップ1の2辺の辺縁に対し直角
に交叉させ、その交叉位置において辺縁と平行な向きに
電源端子6a、 6bが設けられている。On the other hand, the power supply wiring 5 is connected to the power supply wiring 6 by a through hole 5a near a corner of the semiconductor chip l. The power supply wiring 6 is formed into an L-shape 7 when viewed from above, and its both ends intersect at right angles to the edges of the two sides of the semiconductor chip 1, and the power supply lines are connected parallel to the edges at the crossing positions. Terminals 6a and 6b are provided.
このような接地端子4a、 4b、電源端子6a、 6
bは具体的には示さないが半導体チップ1の4隅につい
ても実質的に同し態様で設けられている。Such ground terminals 4a, 4b, power terminals 6a, 6
Although b is not specifically shown, the four corners of the semiconductor chip 1 are also provided in substantially the same manner.
而してこのような本発明装置にあっては接地用のポンデ
ィングパッド3a、電源用のポンディングパッド3bは
これに最も近く位置するモジュールセル2の−の隅角部
、例えば第1図に示す如く左上部の隅角部に設けられて
いる接地端子4a、 4b、電源端子6a、 6bとを
配線7,8にて接続することが可能となる。In the device of the present invention, the grounding pad 3a and the power supply pad 3b are located at the negative corner of the module cell 2 located closest to the grounding pad 3a, for example, as shown in FIG. As shown, it is possible to connect the ground terminals 4a, 4b and the power terminals 6a, 6b provided at the upper left corner with wirings 7, 8.
なお上述の実施例はモジュールセル2の4隅に夫々各2
箇の接地端子4a、 4b、電源端子6a、 6bを設
けた構成につき説明したが、何らこれに限るものではな
くいずれか2箇所の隅部又はいずれか3箇所の隅部に設
けてもよいことは勿論である。In addition, in the above-mentioned embodiment, two
Although the configuration has been described in which the grounding terminals 4a, 4b and the power terminals 6a, 6b are provided, the present invention is not limited to this and may be provided in any two corners or any three corners. Of course.
以上の如く本発明にあっては接地端子、電源端子を夫々
複数箇設けることとしたから、モジュールセルの接地端
子、電源端子とポンディングパッドとの間を接続する配
線の自由度が大きく、配線自体の長さを大幅に短縮する
ことが出来て配線のインピーダンスを低減出来、ノイズ
耐性の向上を図れるなど本発明は優れた効果を奏するも
のである。As described above, in the present invention, since a plurality of ground terminals and a plurality of power supply terminals are provided, there is a large degree of freedom in wiring to connect between the ground terminal and power supply terminal of the module cell and the bonding pad. The present invention has excellent effects, such as being able to significantly shorten the length of the wire, reducing wiring impedance, and improving noise resistance.
第1図は本発明装置の模式的平面図、第2図は第1図の
A部分の拡大図、第3図は従来装置の模式的平面図、第
4図は第3図のB部分の拡大図である。
1・・・半導体チップ 2・・・モジュールセル3a
・・・接地用のポンディングパッド 3b・・・電源
用のポンディングパッド 4・・・接地配線 5.
6・・・電源配線 7.8・・・配線
なお、図中、同一符号は同一、又は相当部分を示す。Fig. 1 is a schematic plan view of the device of the present invention, Fig. 2 is an enlarged view of section A in Fig. 1, Fig. 3 is a schematic plan view of the conventional device, and Fig. 4 is an enlarged view of section B in Fig. 3. It is an enlarged view. 1... Semiconductor chip 2... Module cell 3a
...Ponding pad for grounding 3b...Ponding pad for power supply 4...Grounding wiring 5.
6... Power supply wiring 7.8... Wiring In the drawings, the same reference numerals indicate the same or equivalent parts.
Claims (1)
箇備えた半導体集積回路において、前記モジュールセル
の電源端子、接地端子を夫々複数個設けたことを特徴と
する半導体集積回路装置。(1) A semiconductor integrated circuit device comprising one or more module cells having a predetermined function, characterized in that a plurality of power supply terminals and a plurality of ground terminals are provided for each of the module cells.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32180389A JPH03181149A (en) | 1989-12-11 | 1989-12-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32180389A JPH03181149A (en) | 1989-12-11 | 1989-12-11 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03181149A true JPH03181149A (en) | 1991-08-07 |
Family
ID=18136588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32180389A Pending JPH03181149A (en) | 1989-12-11 | 1989-12-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03181149A (en) |
-
1989
- 1989-12-11 JP JP32180389A patent/JPH03181149A/en active Pending
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