JPH03181817A - Counter apparatus - Google Patents

Abstract

PURPOSE:To realize correct counting by providing a CPU to which two signals of different phases and output signals of a first and a second FF circuits are inputted thereby to add or subtract in accordance with the state of the inputted signals. CONSTITUTION:Signals IN-A and IN-B are inputted to clock input terminals CK of FFs 10, 11 through filters comprised of a resistance R and a capacitor C, respectively. Signals IN-B and IN-A are inputted to data input terminals D of the FFs 10, 11, and signals IN-A and IN-B are inputted to reset terminals R of FFs 10, 11. When it is detected that a signal of H level is inputted to an interrupting input terminal INT0, it is checked whether an input port terminal P10 is in the H level, and a terminal P11 is in the L level. If this condition is satisfied, the value of a counter constituted of a CPU 20 is increased. On the contrary, when an interrupting input terminal INT1 is detected to be in the H level, if the condition that the terminal P10 is L level and the terminal P11 is H level is found satisfactory, the value of the counter of the CPU 20 is decreased. A subtracting pulse is not inputted to the subtracting result and therefore, the result is correct.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter device that counts two-phase phase difference count inputs.

[Prior Art] Conventionally, some counter devices perform count input control using a central processing unit (hereinafter referred to as CPU) in order to configure the device at a low cost. In order to achieve lower prices,
The number of circuit components other than the CPU must be minimized.

FIG. 4 is a timing chart for explaining the counting operation of the two-phase phase difference counting input. For example, - side signal I N
If the other signal INA is at H level when the signal IN-B falls, it is added, and when the signal IN-A falls, the signal INA is added.
Signal processing was performed so that if N-B was Hl/Bell, it would be a subtraction.

[Problem 8 to be solved by the invention] In the conventional counter device as described above, when an addition process is first performed and then a subtraction process is performed, the count is calculated by the fall of the signal INA in the part marked *. There was a problem in that the numerical value "7" was subtracted and the counted value became "6", resulting in erroneous counting (subtraction).

This invention was made to solve this problem, and is designed to prevent erroneous counting even when the two-phase phase difference counting input changes from addition to subtraction, or vice versa. The object of the present invention is to provide a counter device.

[Means for Solving the Problems] A counter device according to the present invention inputs one of two signals having different phases as a clock signal, inputs its inverted signal as a reset signal, and further inputs the other signal as a reset signal. A first flip-flop circuit inputs as a data signal, the other of the two signals with different phases is input as a clock signal, its inverted signal is input as a reset signal, and one signal is input as a data signal. A second flip-flop circuit that inputs two signals with different phases, an output signal of the first flip-flop circuit, and an output signal of the second flip-flop circuit, and performs addition or addition depending on the state of these signals. It has a central processing unit that performs subtraction processing.

[Function] In the present invention, for example, the first flip-flop circuit outputs an addition count pulse, and the second flip-flop circuit outputs a subtraction count pulse.

Then, the central processing unit performs an addition operation or a subtraction operation in accordance with the input of these addition count pulses or subtraction count pulses.

[Embodiment] FIG. 1 is a block diagram showing the hardware configuration of a counter device showing an embodiment of the present invention. In the figure, (10)
and (11) is a D-type flip-flop circuit (hereinafter simply F
F), and (20) is the CPU.

A resistor R is connected to the clock input terminal CK of F F (10).
and a signal IN- through a filter consisting of a capacitor C.
A is input, a signal IN-B is input to the data input terminal, and IN-^ is input to the reset terminal R. FF(
A signal IN-B is inputted to the clock input terminal CK of 11> via a filter consisting of a resistor R and a capacitor C, a signal INA is inputted to the data input terminal, and a signal IN-B is inputted to the reset terminal R. -8 is input.

Interrupt input terminal INTO, lN of CPU (20)
Signals IN-^ and IN-B are input to Tl, and input port terminal PIG.

For pH, F F (to), (11) output QA, Q
B inputs.

Figure 2 shows 90 inputs to F F (10) and (11).
It is a timing chart showing the timing of two signals IN-^ and IN-8 having different phases and the output QA and QB timing of FFs (11) and (12).

Next, the operation will be explained. F F (10) is the signal I
When NA becomes H level and is input as a clock signal to the clock input terminal (J), the signal IN input to the data input terminal at the rise of NA
−[3 (H level) is latched and the output signal QA (H level) is latched.
level). Then, when the signal IN-A becomes L level and the reset terminal R is input, the output signal QA
is reset to L level. In this way, the output signal QA goes high and low in synchronization with the signal INA.
level, resulting in a pulse waveform as shown in the figure.

At this time, the FF (11) receives the signal IN-B at its clock terminal CK, and the signal IN-B at its data input terminal.
^ is input, but since the level of signal IN-B at the rise of signal IN-B is L level, output signal QB
will continue to be at L level.

Next, when shifting from addition counting to subtraction counting, the phase relationship between the signals IN-^ and IN-B is opposite, that is, the signal I
The phase relationship is such that NA leads IN-B by 90 degrees. F F (1G) has a signal IN-A input to its black terminal CK, and a signal IN-B to its data input terminal.
is input, but the signal I at the rising edge of the signal IN-A
Since the level of N-8 is L level, the output signal Q^ continues to be at L level.

F F (11) is a signal that is input to the data input terminal at the rising edge of the signal I N-B when the signal I N-B becomes H level and is input as a clock signal to the clock input terminal CK. It latches IN-A (H level) and outputs it as an output signal QB (H level).

Then, the signal IN-B becomes L level and the reset terminal R
When input, the output signal QB is reset and becomes L level. In this way, the output signal QB is the signal IN-B
It becomes H level and L level in synchronization with , resulting in a pulse waveform as shown in the figure. This output signal QB becomes a pulse signal for subtraction counting as described later, but as shown in the figure, in the conventional method, there is no subtraction pulse in the time range where erroneous counting occurs.
It can be seen that miscounting can be prevented.

On the other hand, the CPU (20) receives signals IN-A and IN-8.
is input as an interrupt signal, and F F (10)
, (11) are inputted as addition pulses or subtraction pulses, and are processed as follows.

First, the addition operation will be explained. FIG. 3(A) is a flowchart showing the operation of the addition operation.

First, it is determined whether an H level signal is input to the interrupt input terminal INTO (81), and if it is determined that the signal is at H level, the input port terminal PlO is at H level and PIL is at L level. It is determined whether or not (S2). If this condition is satisfied, then the CPU
Add the counter configured by (20) (
S3〉. This addition calculation process is performed in step (81).

Since the addition operation is performed when the condition (S2) is satisfied, the addition operation is performed in the addition area shown in FIG.

Next, the subtraction operation will be explained. FIG. 3(B) is a flowchart showing the operation of the subtraction operation.

First, it is determined whether an H level signal is input to the interrupt input terminal lNTl (S4). If it is determined that the signal is at the H level, the input port terminal P1 is at the L level and the pH is at the H level. Determine whether (
S5〉. If this condition is satisfied, then CPU (
20) is subtracted from the counter configured by (S6
〉. Since this subtraction operation is performed when the conditions of steps (84) and (S5) are satisfied, the subtraction operation is performed in the subtraction area shown in FIG. The result of the subtraction operation is correct because the subtraction pulse is not input as in the conventional case, which causes erroneous counting when transitioning from the addition operation to the subtraction operation.

By the way, in the above embodiment, an example was explained in which a transition is made from an addition operation to a subtraction operation, but the same process is performed when a transition from a subtraction operation to an addition operation is performed, so that a subtraction pulse that causes an erroneous count is not input. Therefore, the counting result is correct.

[Effects of the Invention] As described above, according to the present invention, one of the two-phase phase difference counting inputs is synchronized with one signal and the other signal is latched, so that when transitioning from addition operation to subtraction operation, Alternatively, when transitioning from a subtraction operation to an addition operation, a counting pulse that causes erroneous counting is not generated, and accurate counting can be performed.

[Brief explanation of drawings]

ff11 is a block diagram showing the hardware configuration of a counter device according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the FF in FIG. 1, and FIGS. A flowchart showing the operation of the subtraction operation, and FIG. 4 is a timing chart for explaining the operation of the conventional counter device. In the figure, (10) and (11) are FFs, and (20) is a CPU.

Claims (1)

[Claims] A first flip-flop circuit receives one of two signals with different phases as a clock signal, inputs its inverted signal as a reset signal, and further inputs the other signal as a data signal; a second flip-flop circuit which inputs the other signal of the two signals as a clock signal, inputs its inverted signal as a reset signal, and further inputs one signal as a data signal; 1. A counter device comprising: a central processing unit that inputs an output signal of a first flip-flop circuit and an output signal of a second flip-flop circuit, and performs addition or subtraction processing according to the states of these signals.