JPH03182969A - Method for constituting control signal of logical circuit - Google Patents

Abstract

PURPOSE:To freely combine necessary resources so as to obtain an optimum circuit by connecting a control signal and a controlled terminal, both of which have the same identification names, and constituting a logical device composed of a control circuit and a data path circuit. CONSTITUTION:A data path circuit extension part 12, a control synthesis part 13 and a control signal connection part 14 are provided. For generating the control circuit in which the micro program of a logical gate level is set to be a constitution element from the function specification of the control circuit, the identification name is given to the control signal to be outputted. For generating the data path circuit in which hierarchical structure is extended and a logical gate is set to be the constitution element, the identification name is given to the controlled terminal, connecting the control signal and the controlled terminal, both of which have the same identification names, and a logical circuit composed of the control circuit and the data path circuit is constituted. Thus, the resources required for a data transfer operation can freely be combined and the optimum circuit can be constituted even if there is no discription of minute circuit constitution excepting description representing the connection of the data path circuits and description of a data transfer control procedure.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to an automatic design system for a digital logic device that receives as input a description of a functional specification whose description has a higher level of abstraction than the logic gate level and assembler level. The present invention relates to a method of configuring control signals between a control circuit and a data path circuit that is a controlled circuit when synthesizing a logic circuit whose components are lower-level logic gates or bit pattern-level microprograms based on functional specifications.

[Conventional technology]

Conventionally, in automatic design systems for digital logic devices, it has been difficult to configure control signals between a control circuit consisting of a logic gate or bit pattern level microprogram and a data path circuit controlled by the control circuit. Various methods have been proposed for this purpose.

Documents on such automatic design systems for digital logic devices include, for example, A., C., Parker et al.
al 'Automated 5ynthesis
of D+digital Systems'
IEEE Design & Te5tpp
.

75-81 Nov, 1984.

FIG. 14 is a diagram showing the functional specifications of a digital logic device using a two-layer description using the first conventional method.

Traditionally, as a method of configuring control signals, the functional specifications of the control circuit and the functional specifications of the data path circuit are unified in a hierarchical block diagram as shown in Figure 14, and the control signals are explicitly specified. , there is a known method for configuring control signals for logic circuits by developing a hierarchy from these descriptions.

In the figure, the functional blocks are divided into functions according to their functions, and the upper part of Fig. 14 shows a description showing the connections between the functional blocks using the functional blocks as constituent elements. . Such a description is called a higher level description 141. In particular, if there is no higher level hierarchy than the corresponding description, it is called the highest level description. Further, in the middle and lower parts of FIG. 14, detailed descriptions of the functions of each functional block are shown. These are called lower descriptions 142, 143, and 144.

The upper layer description 141 includes a control circuit represented by a functional block, data path circuits 1 and 2, a data path connecting the data path circuits, and control signals 1 .
It is composed of 2.

Further, a detailed description 142 of the function of a functional block representing a control circuit is composed of three logic circuits at the logic gate level and control signals 1.2 output from the logic circuits. This description of the control circuit shows that control signals 1 and 2 are sequentially output as the signals propagate from the right side to the left side of each logic circuit.

A detailed description 143 of the data path circuit 1 includes three logic circuits at the logic gate level, a signal line connecting them, a data path BUS output from one logic circuit, and the logic circuit. It is composed of a signal line for a control signal l to be controlled.

A detailed description 144 of the data path circuit 2 includes two logic circuits at the logic gate level, a signal line connecting them, and a data path B input to one logic circuit.
US and a signal line for control signal 2 that controls the logic circuit.

In this way, in the conventional method of describing functional specifications in which functions are described hierarchically, control signals are explicitly specified and unless they are directly described in the diagram, they cannot be written in a logic circuit whose components are at the logic gate level. could not be configured.

FIG. 15 is a diagram of a logic circuit developed from the functional specifications of FIG. 14.

When the hierarchically described functional specifications shown in FIG. 14 are developed into a description representing the connection configuration of a group of logic circuits at the logic gate level, the result is as shown in FIG. 15.

In this diagram, three logic circuits at the logic gate level belonging to the data path circuit 1, two logic circuits at the logic gate level belonging to the data path circuit 2, three logic circuits at the logic gate level belonging to the control circuit, and It consists of a data path BUS and control signals 1 and 2.

FIG. 16 is a hardware configuration diagram of a conventional automatic design system for digital logic devices.

The automatic design system develops a hierarchically described functional specification as shown in FIG. 14 into a logic circuit having lower-level logic circuits as components, as shown in FIG.

The functional description storage file 164 is a file that stores the functional specifications of a logic circuit described in a hierarchical manner as shown in FIG. This is a file that stores a description of a digital logic device composed of logic circuits.

The main storage device 162 reads a program necessary for the processing of the CPU 161, for example, a description of the functional specifications stored in the functional description storage file 164 from the description input unit 163,
A read/write program 1621 for storing the logic circuit description developed from the functional specification in the logic circuit description storage file 165, and a hierarchical expansion processing program 1622 for developing the functional specification into a logic circuit at the logic gate level.
etc. are memorized.

FIG. 17 is a processing flowchart of the automatic design system shown in FIG. 16.

Hierarchical expansion processing program for conventional automatic design system 16
As shown in FIG. 17, the processing carried out by 22 consists of substituting a higher-level description with a lower-level description to detail a functional block and developing it into a logic circuit at the logic gate level.

First, step 170 extracts the highest level description from the function descriptions stored in the function description storage file 164.
), it is determined whether one or more functional blocks belong to the extracted description (step 170). As a result, if the functional block belongs, one lower description representing the detailed functional specifications of the relevant functional block is extracted, and the process returns to step 171 (step 172). If no functional blocks belong to the hierarchy, it is determined whether the corresponding hierarchy is at the highest level (step 173), and if it is at the highest level, the process is terminated. If it is not the most binary value, the process returns to the level one level lower and replaces the description in the description of that layer, that is, a detailed description of the functional block (step 74).

FIG. 18 is a diagram showing the description of functional specifications using the second conventional method.

Conventionally, as a second method, as shown in FIG. 18, the operation of the procedure for creating a control signal that controls data transfer between data path circuits is described as a detailed lower description 182 of the control circuit. There is.

That is, each control operation 1.2 of control signal 1 and control signal 2
However, the functional specifications of the data path circuit describe the hierarchical block configuration, specify the control signals explicitly, and develop the hierarchy from these descriptions to create the logic shown in Figure 15. It constituted the control signal of the circuit.

FIG. 18 shows an example in which the functions of a digital logic device are expressed in a two-layer description. In the figure, there is an upper level description 181 that includes functional blocks as components, and lower level descriptions 182, 183, and 18 that detail the functions of each functional block.
4.

The upper layer description 181 is composed of a control circuit represented by a functional block, data path circuits 1 and 2, a data path connecting the pig path circuits, and control signals 1 and 2 from the control circuit. A detailed description 182 of the function of a functional block representing a control circuit is composed of control operations 1.2 representing that control signals 1.2 are sequentially generated.

Also, a lower description 183 detailing the data path circuit 1
consists of three logic circuits at the logic gate level, a signal line connecting them, a data path BUS output from one logic circuit, and a signal line for control signal 1 that controls the logic circuit. . Further, a lower description 184 detailing the data path circuit 2 includes two logic circuits at the logic gate level, a signal line connecting them, a data path BUS input to one logic circuit, and the logic circuit. control line for signal 2; and a control line for signal 2.

FIG. 19 is a hardware configuration diagram of an automatic design system for developing a logic circuit from the functional specifications shown in FIG. 18.

Compared to the configuration of the automatic design system shown in FIG. 16, the automatic design system shown in FIG. 19 stores a logic expansion processing program 1922 instead of the hierarchical expansion processing program 1622, and a new circuit configuration description storage file 196 It is different in that it has been added to.

The logic development processing program 1922 develops the functional specifications described in the control circuit and data path circuit as shown in FIG. 18 into a logic circuit whose components are lower-level logic circuits as shown in FIG. do.

In the figure, a functional description storage file 194 is a file that stores the functional specifications shown in FIG. 18, and a logic circuit description storage file 195 is composed of logic circuits at the lower logic gate level expanded from the functional specifications. A file that stores a description of a digital logic device. moreover,
The circuit configuration description storage file 196 is a file that stores a description specifying the configuration of the logic circuit at the logic gate level referred to by the logic expansion processing program 1922.

The main storage device 192 stores programs necessary for the processing of the CPU l 91, for example, a description of a functional specification stored in a functional description storage file 194 is read from the description human resource section 193, and a description of a logic circuit developed from the functional specification is stored in the main storage device 192. A read/write program 1 for storing a description in the logic circuit description storage file 195 and further reading from the circuit configuration description storage file 196 a description specifying the configuration of the logic gate level logic circuit referred to by the logic expansion processing program 1922.
921 and a logic expansion processing program 1922 that expands the functional specifications to a logic circuit at the logic gate level.

FIG. 20 is a flowchart of the logic expansion processing procedure performed by the logic expansion processing program of the automatic design system shown in FIG. 19.

The processing step in FIG. 20 is different from the processing step in FIG.
) and a control circuit in that a process (206) for creating a logic 1 circuit is added.

First, step 200 of extracting the highest level description from the function descriptions stored in the function description storage file 94.
), it is determined whether one or more functional blocks belong to the retrieved description (step 201), and if a functional block does belong, a lower-level description representing the detailed functional specifications of the corresponding functional block is written. One is taken out and the process returns to step 201 (step 202). 1 functional block
If the hierarchy does not belong to the hierarchy, it is determined whether the hierarchy is the highest (step 203), and if it is the third highest, the process ends. If it is not in the third place, it is determined whether the corresponding description is of a control circuit (step 204).
). If it is not a control circuit, that is, if it is a data path circuit, go back to the third layer and write the following in the description of that layer:
The corresponding functional block is replaced with a detailed description, and the process returns to step 201 (step 205). In addition, when it is a control circuit, one logic circuit is associated with each control operation, and each logic circuit is connected to each other in the order of the control operation, and the output signal of each logic circuit is made to correspond to the control signal. and configure the control circuit. Then, the process returns to the next higher level, replaces the functional block representing the corresponding control circuit in the description of that hierarchy with the detailed description of the control circuit, and returns to step 201 (step 206). Note that one logic circuit in this case is a flip-flop circuit (denoted as FF) having a memory function.

FIG. 21 is a diagram showing the description of functional specifications using the third conventional method.

In FIG. 21, the procedure for data transfer between data path circuits is described as a functional specification description 211, but control signals and data path circuits are created from these descriptions without explicitly specifying control signals. Therefore, a method of configuring control signals for logic circuits is used.

Control operations 1 and 2 in the figure represent the contents controlled by the control circuit for data transfer and the order of control. Here, it is shown that data is transferred from the resource on the left side of '→' to the resource on the right side, and it is also shown that the operations continue in the order in which the flow is described, as in control operations 1 and 2. Further, the resources are logic circuits such as register circuits and arithmetic circuits that constitute the data path circuit, and the circuit configurations of these logic gate level circuits are stored in advance in the circuit configuration description storage file.

FIG. 22 is a hardware configuration diagram of an automatic design system for creating the logic gate level circuit configuration shown in FIG. 15 from the description of the functional specifications shown in FIG. 21.

The automatic design system for digital logic devices shown in FIG.
Input the functional specifications that describe the data transfer procedure of the data path circuit shown in FIG.
24, and after sequentially extracting it and developing it into a logic circuit whose components are lower-level logic circuits,
It is stored in the logic circuit description storage file 225.

That is, the functional description storage file 224 is a file that stores the functional specifications shown in FIG. This is a file that stores the device description. Furthermore, the circuit configuration description storage file 226 is a file that stores a description specifying the configuration of a logic circuit at the logic gate level that is referenced by the logic synthesis processing program 2222.

The main storage device 222 loads a program necessary for the processing of the CPU 221, for example, a description of the functional specifications stored in the functional description storage file 224 from the description input unit 223.
A description of the logic circuit expanded from the functional specifications is stored in the logic circuit description storage file 225, and a description specifying the configuration of the logic circuit at the logic gate level referred to by the logic synthesis processing program 2222 is stored in the circuit configuration description storage file 225.
A read/write program 2221 for reading from 26, a logic synthesis processing program 2221 for developing a logic circuit at a logic gate level from the functional specifications, and the like are stored.

FIG. 23 is a flowchart showing the processing procedure of the logic synthesis processing program in FIG. 22.

15 First, read the functional specification description stored in the functional description storage file 224, associate one FF with each control operation, connect the FFs according to the control operation order,
A control circuit composed of them is created (step 23o). Next, a description of the logic gate level circuit configuration of the resource specified in each control operation is read from the circuit configuration description storage file 225 shown in FIG. 22 (step 231). Next, for each resource specified as the transfer destination by control action, collect the resources specified as the transfer source for that resource, use the resources specified as the transfer source as input, and output the transfer destination. A selector circuit serving as a resource designated by is synthesized, and the output of the control circuit is connected to the control input terminal group of this selector circuit (step 232).

24 and 25 are flowcharts of the detailed processing of steps 230 and 232 in FIG. 23, and FIG. 26 is an explanatory diagram showing the processing procedure of the logic synthesis processing in FIG. 25.

FIG. 24 shows a detailed flow of the processing steps for synthesizing the control circuit. First, one control operation is extracted from the functional specification description (step 240), and one FF corresponding to this control operation is arranged (step 241).

For the control operation of interest, it is determined whether there is an FF corresponding to the immediately previous control operation (step 242).

If there is a corresponding FF, the FF placed in step 241
Connect the input terminal of the FF and the output terminal of the corresponding FF (
Step 243). If there is no corresponding FF, the process returns to step 240. Then, it is determined whether or not there is an unprocessed control operation, and if there is, the process returns to step 240, and if not, the process ends (step 244).

FIG. 25 shows a detailed flow of the process (232) for connecting control signals in FIG. 23.

First, one resource specified as a transfer destination is extracted from the control operation described in the functional specification and placed there (step 250).

Next, from the control operations described in the functional specifications, source resources that transfer data to the destination resource are collected, and the second
6 (step 251).

In FIG. 26(A), one destination resource and two source resources are arranged. Next, selector circuits having as many input terminals and control terminals as there are source resources are arranged as shown in FIG. 26(B) (step 252).
. Next, the output terminals of all source resources and the input terminals of the selector circuits are connected, and the control terminals of the selector circuits and the control signals of the corresponding control circuits are connected as shown in FIG. 26(C). Step 253). Next, the output terminal of the selector circuit and the input terminal of the destination resource are connected (step 254). Then, the existence of unprocessed destination resources is determined, and if there is, step 2
Return to step 50, and if there is no
).

[Problem to be solved by the invention]

As described above, there are three conventional methods for configuring control signals for logic circuits. However, in the first method described above, it is necessary to embody design a1 to the point where the complex control operation that is the function of the control circuit can be expressed by a combination of logic circuits at the logic gate level. There is a problem in that unless all signals between logic circuits and logic circuits are specified explicitly, they cannot be developed into logic circuits at the logic gate level.

In addition, in the second method described above, since the control signal between the control circuit and the pig path circuit is explicitly specified, the operation representing the control function must be detailed to the transmission and reception of the control signal, or the logic at the logic gate level. There is a problem that it cannot be expanded into a circuit.

Furthermore, in the third method described above, only circuits whose configuration at the logic gate level has been determined in advance can be used as resources as data path circuits. The problem is that it is impossible to create a configuration.

An object of the present invention is to solve these conventional problems, and to perform data transfer operations without a detailed description of the circuit configuration other than the description representing the connections between data path circuits and the description of the data transfer control procedure of the control circuit. An object of the present invention is to provide a method for configuring control signals for a logic circuit, which allows configuring an optimal circuit by freely combining necessary resources.

[Means for Solving the Problems 1] In order to achieve the above object, a control signal configuration method for a logic circuit according to the present invention describes the operation of data transfer between the data path circuits as a functional specification of the control circuit, As the functional specifications of the data path circuit, the connections between the logic blocks are described, and from the functional specifications of the control circuit, an identification name is given to the control signal output from the control circuit to specify that it is a control signal. , is expanded to the above lower level control circuit, and based on the functional specifications of the above data path circuit, the above identification name is given to the controlled terminal that receives the above control signal, and the same is expanded to the above lower level data path circuit. The present invention is characterized in that the control signal having the identification name and the controlled terminal are connected to form a digital logic device comprising the lower level control circuit and the lower level data path circuit.

[For production]

In the present invention, (a) the functional specifications of the control circuit are described as operations, and separately, the functional specifications of the data path circuit are described as a hierarchical block configuration without representing control signals from the control circuit. . (b) When creating a control circuit whose components are microprograms at the logic gate or bit pattern level based on the functional specifications of the control circuit, an identification name is given to the control signal output from the control circuit. (c) At the same time, when creating a data path circuit whose constituent elements are logic gates by developing a hierarchical structure from the functional specifications of the data path circuit, an identification name is assigned to the controlled terminal that receives the control signal output from the control circuit. Give. (d) Then, a control signal and a controlled terminal having the same identification name are connected to form a logic circuit of a digital logic device including a control circuit and a data path circuit.

This eliminates the need for detailed circuit configuration descriptions other than the descriptions representing the connections between data path circuits and the data transfer control procedures of the control circuit, and allows the user to freely combine the resources necessary for data transfer operations. A suitable circuit can be constructed.

〔Example] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a diagram showing a description of functional specifications in the present invention.

FIG. 3 shows an example in which the functions of a digital logic device are expressed in a two-layer description, with an upper layer description 31 that includes functional blocks as constituent elements, and a lower layer description 31 that details the functions of each functional block. 32, 33, and 34 are listed.

The upper layer description 31 is composed of a control circuit represented by a functional block, a data path circuit 1.2, and a data path connecting the data path circuits. In the lower description 32 detailing the control circuit, the control operation 1.2 represents the content controlled by the control circuit for data transfer and the order of control. The content of the control indicates that data is transferred from the resource on the left side of →′ to the resource on the right side,
The order of control indicates that the operations continue in the order in which the flow is described, such as control operations 1 and 2. Here, resources are
These are logic circuits such as register circuits and arithmetic circuits that make up the data path circuit, and unlike the conventional third method, the circuit configuration at the logic gate level is described when detailing the function of the data path circuit. do.

On the other hand, a lower description 33 detailing the data path circuit 1 is composed of a logic circuit of two resources at the logic gate level, a data path circuit BUS, and a signal line connecting them. Further, a lower description 34 detailing the data path circuit 2 is composed of a logic circuit of one resource at the logic gate level, a data path BUS, and a signal line connecting them. In this way, in the description of the functional specifications of the present invention, the functional specifications are described using different notations for the control circuit and the data path circuit.

FIG. 2 is a hardware configuration diagram of an automatic design system for digital logic devices showing one embodiment of the present invention.

This automatic design system develops the functional specifications of the control circuit and data path circuit as shown in FIG. 3 into a logic circuit whose constituent elements are lower-level logic circuits as shown in FIG.

The hardware configuration includes a CPU 21, a main storage device 22, a description input section 23, a functional description storage file 24, a logic circuit description storage file 25, and a temporary storage file 26. The main storage device 22 also stores a control connection processing program 222 generated according to the present invention.

Note that the functional description storage file 24 is a file that stores functional specifications as shown in FIG. 3, and the logic circuit description storage file 25 is composed of logic circuits at the lower logic gate level developed from the functional specifications. The time storage file 26 is a file that temporarily stores data of the processing process of the control connection processing program 222.

The main storage device 22 stores a program necessary for the processing process of the CPU 21, for example, a description of a functional specification stored in a functional description storage file 24 is read from the description input section 23, and a logic circuit developed from the functional specification is stored in the main storage device 22. A read/write program 221 for storing the memory in the logic circuit description storage file 25 and temporarily storing the data of the processing process of the control connection processing program 222.
and a control connection processing program 222 for developing a logic circuit at the logic gate level from the functional specifications.

FIG. 1 is a functional block diagram of a control connection processing program showing one embodiment of the present invention.

As shown in FIG. 1, the control connection processing program 222 stored in the main storage device 22 of FIG. a creation unit 11; a data path circuit expansion unit 12 that expands the description of a functional block to be processed into a detailed logic gate level logic circuit description when the description is a data path circuit; In the case of
Then, there is a control circuit synthesis unit 13 that synthesizes detailed descriptions of logic circuits at the logic gate level, a control signal connection unit 14 that connects these two types of logic circuits with each other with control signal lines, and a processing unit 11 of these four types. 14.

After the hierarchical tree creation unit 11 creates a hierarchical tree and stores it in the -time memory file 26, the topmost hierarchy is taken out, and the control signal connection unit 14 connects the control signal line between the data path circuit and the control circuit. Then, the data path circuit expansion unit 12 replaces the functional block with a detailed description, and then the control circuit synthesis unit 13 creates a control circuit, and converts the functional block representing the control circuit into a detailed control circuit. Replace with the description of

FIG. 4 is a flowchart showing the processing procedure of the execution control unit in FIG. 1, and FIG. 5 shows two types of data structures representing a hierarchical tree and an example of a hierarchical tree represented by them. It is a diagram.

First, the hierarchical tree creation unit 11 uses the read/write program 221
A hierarchical tree as shown in FIG. 5 is created from the functional specifications stored in the functional description storage file 24 read by step 40, and is stored in the time storage file 26 (step 40).
).

FIG. 5(A) shows a data structure corresponding to one description that includes functional blocks as description elements. A description that includes a functional block as a description element corresponds to a description at the top or middle level. This data structure includes a description name 51 for identifying the applicable description from other descriptions, a description level 52 for specifying the hierarchy of the applicable description, and a functional block for specifying the functional blocks that are the constituent elements of the applicable description. It consists of a list of 53 names. Specifically, description level 52 is:
m specifies a description at the top or middle level, and C specifies a description at the lowest level, which will be described later.

FIG. 5B shows a pig structure corresponding to one description in which all description elements are logic circuits at the logic gate level.

This corresponds to the lowest level description. This data structure has a descriptive name 51 and a descriptive level 5 that have the same role as (A).
2, and a function name 54 indicating whether the corresponding description specifies the function of a control circuit or the description of a data path circuit. Specifically, the function of the control circuit is specified by ctl, and the function of the data path circuit is specified by pth.

Figure 5(C) shows the description of the functional specifications shown in Figure 3.
An example of a hierarchical tree expressed using the above two types of data structures is shown. Here, 55 to 58 correspond to descriptions a to d shown in FIG. 3, respectively. A solid line with an arrow (hereinafter referred to as a hierarchical reference line) represents a reference relationship between descriptions, that is, a hierarchical relationship, and the description indicated by the arrow is a description lower than the description at the root point of the arrow. It represents that.

The end of the reference line is called ``the hierarchy reference line points to,'' and the source of the reference line is called ``the hierarchy reference line points out.'' For example, 55 d
The hierarchical reference line extending from 56 to 56 indicates that the functional block specified by function block name d is a descriptive element of the description with descriptive name a, and its detailed description is the descriptive name d in 56. is specified. That is, the upper layer is a, and one of the lower layers is d. Therefore, the description with the highest rank is one that does not have a hierarchy reference line that points to the data structure of the corresponding description, but has one or more hierarchy reference lines, and the description in the middle hierarchy is the one that has one or more hierarchy reference lines pointing to the data structure of the corresponding description. There is one hierarchical reference line that points to the data structure of the description, and one or more hierarchical reference lines appear.

The above is the explanation of the hierarchical tree creation process in step 40 of FIG. In FIG. 4, this hierarchical tree is then searched to find the topmost description and extract that description (step/11). There is 1 function block in the extracted description.
Step 42)
If the functional block belongs, one of the lower-level descriptions representing the detailed functional specifications of the relevant functional block is extracted, and the process returns to step 42 (step 43). on the other hand,
If no functional blocks belong to it, it is determined whether the corresponding layer is at the top level (step 44); if it is at the top level, the control signal connection section 14 is used to connect the data path circuit and the control circuit. They are connected by control signal lines, the resulting logic gate level description is stored in the logic circuit description storage file 25, and the process ends (step 45). Furthermore, if it is not ranked first, it is determined whether the corresponding description is for a control circuit (step 46). If it is not a control circuit, that is, if it is a data path circuit, return to the next higher layer and use the data path circuit development unit 12 to replace the description of that layer with a detailed description of the corresponding functional block ( Step 48), return to step 42. In addition, if it is a control circuit, create the control circuit using the control circuit synthesis unit 13, return to the first layer, and write the functional block representing the corresponding control circuit in its details in the description of that layer. (Step 47)
), return to step 42.

FIG. 6 is a flowchart showing the processing procedure of the control circuit synthesis section in FIG. 1, and FIG. 7 is a flowchart showing the processing procedure of the control circuit synthesis section in FIG. FIG.

The control circuit synthesis unit 13 first extracts one control operation from the description of the functional specifications of the control circuit (step 60). One FF corresponding to the control operation is arranged as shown in FIG. 7, and a unique control signal name different from other control signals is given to the signal line coming out from the output terminal of the corresponding FF (step 61).

The control circuit in FIG. 7 includes a signal line connecting a group of FFs corresponding to each control operation and one FF corresponding to sequential changes in the control operation, and a control circuit branching from the output terminal of each FF. It consists of signals. Here, the control action changes from 1 to 2. For example, control operation J
The change from to 2 connects the output of the FF corresponding to control operation 1 and the input of the FF corresponding to control operation 2, and
The circuit is configured such that F is ONL, and then the latter FF is turned ON.

The above is an explanation of the operation of step 61 in FIG.

In FIG. 6, path data of a data structure is created based on the control operation of interest (step 62).

FIG. 8 is a diagram showing the data structure of path data and an example of its application.

FIG. 8(A) shows the data structure of path data. This data structure is created for each destination resource for data transfer specified in a control operation, and contains the destination resource name 81 that specifies the corresponding destination resource, the source resource for that destination resource, and the information for the transfer. and one or more pairs of control signals (hereinafter referred to as source data). If path data for the destination resource of the control operation of interest already exists, source data created from the control operation is added to the corresponding path data.

Further, FIG. 8(B) is path data corresponding to the description of the functional specifications of the control circuit as shown in FIG. 3 (corresponding to the description of the description amount d). That is, the path data 87 corresponding to control operation 1 is the destination resource name 81
is BUS, source resource name 82 is A, control signal 83 is ct
It is l I. Further, in the path data 88 corresponding to control operation 2, the destination resource 81 is C, the source resource name 82 is BUS, and the control signal 83 is ctl2.

The above is the explanation of the path data creation process in step 62 in FIG. In FIG. 6, next, for the control operation of interest, it is determined whether there is an FF corresponding to the immediately previous control operation (Step 2 (Tub 63)). If there is a corresponding FF, step 61 is performed. The input terminal of the arranged FF and the output terminal of the corresponding FF are connected (step 64). If there is no corresponding FF,
Return to step 60. Next, it is determined whether or not there is an unprocessed control operation, and if there is, the process returns to step 60, and if not, the process ends (step 65).

FIG. 9 is a flowchart showing the processing procedure of the data path circuit development section in FIG. 1, FIG. 1O is a data structure diagram of path pair data and an example thereof, and FIG. FIG. 3 is an explanatory diagram showing an example of a data path circuit replacement procedure.

As shown in FIG. 9, the data path circuit expansion unit 12 first determines from the description of the functional specifications of the processing target that out of the functional blocks that are mutually connected by signal lines, signal lines for connection are output from the output terminals. As shown in Figure 1, a functional block or a logic circuit at the logic gate level is used as a destination resource, and a logic circuit at the logic gate level or a functional block whose input terminal has a signal line for connection is used as a source resource. Create path pair data (step 90
).

The path pair data shown in FIG. 1O (A) is a pair of destination resource name 101 and source resource name 102 that specify the destination resource and source resource of data transfer specified in the functional specification description of the data path circuit. It consists of

FIG. 10(B) shows an example of path pair data corresponding to the amount of description in the functional specification description of FIG. 3.

That is, in the upper diagram of (B), the destination resource name 101 is data path BUS, and the source resource name 1 is
Logic circuit A is designated as 02. Further, in the lower diagram of (B), data path BUS is specified as the destination resource name 101 and logic circuit B is specified as the source resource name 102.

The above is an explanation of the path pair data creation process in step 90 of FIG. In FIG. 9, next, with reference to the path pig created by the control circuit synthesis unit 13, a control signal for the destination resource and source resource pair of the path pair data is determined, and the corresponding control signal is transferred to the gate signal. −
As shown in FIG. 11, a selector circuit called No. 1 is placed in the description of interest (step 91).

FIG. 11(A) is an extracted description of the description name from the functional specification description of FIG. 3. Figure 11 (A)
From the description, path pair data as shown in FIG. 10(B) is created. On the other hand, path data as shown in FIG. 8(B) has already been created. In these examples, the control signal for the destination resource and source resource pair is ctl], and the control signal for the destination resource and source resource pair is
A selector circuit as shown in B) is arranged between the destination resource BUS and the source resource A.

The above is the explanation of the selector circuit creation process in step 91 in FIG. In Figure 9, the corresponding function block in the description above the description being focused on is replaced with the description created in the previous process, and the function block connected to the input/output terminal of the corresponding function block is also replaced. The signal line connected to the input/output terminal 5 in the replaced description is connected (step 92).

FIG. 11(C) shows an example of the result of arranging the functional blocks.

FIG. 12 is a flowchart showing the processing procedure of the control signal connection section in FIG. 1, and FIG. 13 is an explanatory diagram showing the control signal connection procedure.

The control signal connection unit 14 finds a destination resource in which two or more source resources are associated with one destination resource based on the previously created path pigeon, and inputs it to the corresponding destination resource. An OR circuit as shown in FIG. 13(B) is arranged in the selector circuit (step 120). Next, terminals having the same control signal name in the description of the processing target are connected as shown in FIG. 13(B) (step 121).

In FIG. 13(A), the control circuit synthesis unit 13 and data path circuit expansion unit 12 of FIG. The result of placing the logic circuit is shown. As shown in the selector circuit of FIG. 13(B), two source resources A and B are selected for the destination resource BUS.
Therefore, the output of the original selector circuit (the selector circuit shown in FIG. 13(A)) and the destination resource B[J
An OR circuit is placed between the selector circuit and the corresponding input terminal of the OR circuit with a signal line.
The output terminal of the circuit and the input terminal of the destination resource BUS are connected by a signal line. In addition, in the case of a resource that is directly connected to a destination resource without going through a selector circuit, connect the output terminal of the relevant resource and the corresponding input terminal of the OR circuit with a signal line, and connect the output terminal of the OR circuit with the output terminal of the OR circuit. It is connected to the input terminal of the destination resource BUS by a signal line.

In this way, in this embodiment, (a) the functional specifications of the control circuit are described as operations, and the functional specifications of the data path circuit are described separately as a hierarchical block configuration without representing the control signals from the control circuit. Describe. (b) When creating a control circuit including logic gates as constituent elements from the functional specifications of the control circuit, an identification name is given to the control signal output from the control circuit. (c) At the same time, when creating a data path circuit whose constituent elements are logic gates by developing a hierarchical structure from the functional specifications of the data path circuit, connect the control signal output from the control circuit and the controlled terminal. . (E)
In this way, a logic circuit of a digital logic device consisting of a control circuit and a data path circuit is constructed.

In the embodiment, a case has been described in which the control circuit is configured by a combination of logic circuits, but the present invention can be applied in exactly the same way even if the control circuit is configured by a microprogram. That is, by creating path data as shown in FIG. 8(B) in the control signal created from the microprogram, exactly the same effect can be obtained.

[Effects of the Invention] As described above, according to the present invention, in an automatic design system for a digital logic device that inputs a description of a functional specification whose description has a higher level of abstraction than the logic get level and assembler level, It is possible to configure an optimal circuit by freely combining the resources necessary for data transfer operations even without a detailed description of the circuit configuration other than a description of the connections and a description of the transfer control procedure of the control circuit. be.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a control connection processing program showing one embodiment of the present invention, FIG. 2 is a hardware configuration diagram of an automatic design system for digital logic devices showing one embodiment of the present invention, and FIG. FIG. 4 is a flowchart showing the processing procedure of the execution control unit of the control connection processing program in the present invention, and FIG. 5 is a diagram showing the description of the functional specifications in the present invention. Figure 6 is a flowchart showing the processing procedure of the control circuit synthesis section of the control connection processing program, and Figure 7 is the logic at the logic gate level created by the processing of the control circuit synthesis section. FIG. 8 is a diagram showing the data structure of path data and an example of its application. FIG. 9 is a flowchart 1 showing the processing procedure of the data path circuit expansion part of the control connection processing program.・、
FIG. 10 is a diagram showing the data structure of path pair data and an example thereof, FIG. 11 is an explanatory diagram showing the data path circuit replacement procedure, and FIG. 12 is a diagram showing the processing procedure of the control signal connection section of the control connection processing program. 13 is an explanatory diagram showing the control signal connection procedure, FIG. 14 is a diagram showing the description of the functional specifications of the conventional first method, and FIG. 15 is developed from the functional specifications of FIG. 14. Figure 16 is a diagram showing the connection configuration of a group of logic circuits at the logic gate level; Figure 16 is a hardware configuration diagram of an automatic design system that inputs the functional specifications in Figure 14;
The figure is a flowchart showing the processing procedure of the hierarchical expansion processing program of the automatic design system shown in Fig. 16, Fig. 18 is a diagram showing the description of the functional specifications of the conventional second method, and Fig. 19 is a flowchart showing the processing procedure of the hierarchical expansion processing program of the automatic design system.
Figure 8 is a hardware configuration diagram of an automatic design system for inputting descriptions of functional specifications, Figure 20 is a flowchart showing the processing procedure of the logic expansion processing program of the automatic design system shown in Figure 19, and Figure 21 is a diagram of the conventional design system. Figure 22 is a diagram showing the description of the functional specifications of method 40 of method 3, Figure 22 is a hardware configuration diagram of an automatic membrane 31 system that manually connects the functional specifications of Figure 21, and Figure 23 is the automatic design of Figure 22. A flowchart showing the processing procedure of the logic synthesis processing program of the system. Figure 24 is a detailed flowchart of the control circuit synthesis processing of the logic synthesis processing of Fig. 23. FIG. 26 is an explanatory diagram showing the procedure of logic synthesis processing. 11: Hierarchical book creation section, 12: Data path circuit expansion section, I
3: Control circuit synthesis section, I4: Control signal connection section, 15: Execution control section, 31: Upper layer description, 32 to 34: Lower description detailing the control circuit or data path circuit, 5
1: Description thread, 52: Description level, 53: Function block name, 54; Function name, 71 to 73: Flip-flop corresponding to control operation, 81: Destination resource name, 82
゜84, Source resource name, 83, 85: Control signal, 87.
88: Path data corresponding to control operation. (C) Figure (Part 2) Figure Figure Control Signal 1 909- Control Signal +11 3 Figure 8 (Part 2) (B) 910- Figure 1 Figure Hole Figure 2 Figure 918- Figure Number 2 Figure 2 (4) Figure 2 (Part 1) Edge

Claims (1)

[Claims] (1) From the functional specifications of the digital logic device, configure a control circuit whose components are logic circuits at the logic gate level or microprograms at the bit pattern level, which are at a level lower than the level of the functional specifications, and logic circuits at the logic gate level. In an automatic design system that creates a data path circuit as an element, the data transfer operation between the data path circuits is described as the functional specification of the control circuit, and the data transfer operation between the logic blocks is described as the functional specification of the data path circuit. Describe the connection, give an identification name to the control signal output from the control circuit to specify that it is a control signal based on the functional specifications of the control circuit, expand it to the lower-level control circuit, and write the data. Based on the functional specifications of the path circuit, the above identification name is given to the controlled terminal that receives the above control signal, and the above control signal and the above controlled terminal that have the same above identification name are expanded to the lower level data path circuit. A method for configuring control signals for a logic circuit, characterized in that a digital logic device comprising the lower level control circuit and the lower level data path circuit is configured by connecting the lower level control circuit and the lower level data path circuit.