JPH03260872A - Low-order development automating system - Google Patents

Abstract

PURPOSE:To select optimum configuration by describing the designation of functions and the designation of configuration for a logic unit and preparing one of a logic circuit with wiring logic and a logic circuit with a microprogram or a logic circuit mixing those both configuration systems according to the designation of the same function by using those descriptions. CONSTITUTION:Based on the designation of the functions for the logic unit storing a file, the logic circuit at a logic gate level is prepared by a logic synthesizing program 39, and the microprogram at a bit pattern level is prepared by a microprogram compiler 38. When preparing the logic circuit at a low-order level from function specification by using a switch to change over the logic synthesizing program 39 and the micorprogram compiler 38 based on the designation of the logic configuration, the logic circuit and the microprogram are prepared while being selected according to the designation of one function. Thus, the optimum logic configuration can be selected.

Description

[Detailed description of the invention] [Industrial Application Field J The present invention relates to a low-level expansion automation method that can describe the function specification and configuration specification of a digital logic device as an automatic design device, and use these to create a logic circuit of wired logic or a logic circuit of microprogram. be. [Conventional technology]

Conventionally, automatic design devices for digital logic devices that take functional specifications as input include, for example, Information Processing Handbook A, Inc., Information Processing Society of Japan, December 20, 1976, published by Ohmsha Co., Ltd., pp. 15. As described in 62 to 15-69, by specifying the functional specifications, the logic circuits whose constituent elements are logic circuits at the lower level of logic gate level and microprograms at the bit pattern level are automatically created. It was something to create. Such a low-level expansion automation device as an automatic design device is expressed by state transitions as shown in FIG. 11, and from the description, logic gate level theory 1]! A circuit was created. This state transition diagram includes descriptions of 5TGI and END that specify the start and end of state transition, and control operations executed by the logical device (for example, data transfer operation control WA:=B:,E:
=F, l, activation of other state transitions that mean activation of other logical devices i=><5TG2>;J, etc.) are divided into fixed time units. Condition 2. . . . It is composed of descriptions of state n and state m, and a description of "transition J representing the progress of the control action, and r transition condition representing the progress condition of the control action." Further, the description of a "state" is composed of a "state name" which is an identification name of the state, and a "control operation" to be executed within the state. Note that in FIG. 11, the transition from state n back to state 1 is a transition for explicitly specifying that the logic device 5TGI is repeatedly activated. Also, state S
The control operation r-><5TG2>;J of Tn specifies starting another state transition 5TG2. FIG. 12 is a data structure diagram for storing the description of the mlll diagram in the lower layer R automation device. FIG. 12(A) is a data structure diagram corresponding to one description unit, and shows whether the relevant description statement indicates the start or end of a state transition (hereinafter referred to as T), or a state control operation. (hereinafter referred to as S)
It consists of descriptive text type J and the corresponding "descriptive text". FIG. 12 (B) is a detailed diagram of a part of the data structure in (A) above, and shows the data structure of "descriptive sentence J" when the descriptive sentence type is T. In other words, this data structure Then, if the corresponding descriptive sentence indicates the start of a state transition, then
Specify a unique name for a set of state transitions, and if the corresponding descriptive statement indicates the end of a state transition, specify END.
It consists of "attributes of descriptive text", "activation signals" which are activation conditions for state transitions, and state names of transition destinations. FIG. 12(C) is a detailed diagram of a part of the data structure in (A) above, and shows the data structure of the "descriptive text" when the descriptive text type is S. That is, this data structure is
It consists of a state name, a control action statement for the relevant state, a transition condition that specifies a destination to transition from the relevant state, and a transition destination. FIG. 13 shows the connections of the logic circuit group at the logic gate level synthesized from the functional specifications of FIG. 11! It is a descriptive diagram showing the configuration. The logic circuit group in this figure is in the states STI, ST2゜...ST
n, logic circuit STI corresponding to STm. ST2. ...STn, STm, and transition condition a. A corresponding logic circuit STn when C becomes true. A timing circuit of an AND circuit that turns on STm, and logic circuits STI, ST2 . ...-5Tn, STm is O
It is composed of a clock signal Ql that provides the timing when the signal becomes N. FIG. 14 is a diagram showing the hardware configuration of a conventional automatic design device for digital logic devices. This automatic design device is a jl! A lower level logic circuit as shown in FIG. 13 is synthesized from the functional specifications expressed by state transitions as shown in FIG. In FIG. 14, the CPU 146 is the description input device 143.
This is a processing device that creates a logic circuit group at the lower logic gate level shown in FIG. 3 from the functional specifications input from the processor. The functional description storage device 144 is a file that stores the functional specifications of the logic circuit shown in the state transitions shown in FIG. 11 in the data structure shown in FIG. This file stores the description of a digital logic device composed of logic circuits at the lower logic gate level synthesized from functional specifications. Main storage device 140
reads a program necessary for the processing of the CPU 146, for example, a description of a functional specification stored in the functional description storage means 144 from the description input device 143, or reads a description of a logic circuit synthesized from the functional specification into the logic circuit description storage device. 14
The logical synthesis processing program, etc. to be stored in 5 is stored therein. FIG. 15 is a flowchart showing the procedure of lower-level development processing by the automatic design device of FIG. 14. First, (i) when the read/write program is activated and a description of the functional specifications is input from the description input device 143, the program converts this functional specification into a data structure as shown in FIG. Store it in the description storage device 144 (step 50).Next, (ii) the logic synthesis processing program is activated to retrieve the function description from the function description storage device 144 and store the corresponding state for each state in the function description. One logic circuit corresponding to the state is placed, and a timing circuit is connected to the set terminal of the corresponding logic circuit. For each transition condition to the state of interest, this timing circuit calculates the logical product of the signal corresponding to the corresponding transition condition and the signal from the output terminal of the logic circuit corresponding to the transition source state, and calculates the logical product for each logical product. (step 51). Next, (fli) it is determined whether there are any unprocessed function descriptions, and if there are any unprocessed ones, the process returns to step 51 to create a logic circuit, but if there are no unprocessed ones, proceed to the next step (step 52), (tv) The logic synthesis processing program ends the processing by storing the synthesis result in the logic circuit description storage device 145 (step 53). Note that the process shown in FIG. 15 is performed when a logic circuit is created from a functional specification description using a conventional low-level deployment automation device, but in the case of a device that creates a microprogram instead of a logic circuit, the process described above In FIG. 14, a microprogram synthesis processing program is provided instead of the logic synthesis processing program. Also in FIG. 5, a microprogram is created in place of the logic circuit (step 51), and the created microprogram is stored in a file (step 53).
). [Problems to be Solved by the Invention] As mentioned above, in conventional automatic design devices, the lower-level description expansion program, which is a means of describing functional specifications, is divided into two parts: one for logic circuit synthesis and one for microprogram synthesis. . As a result, it is not possible to create the logical configuration of both a logic circuit and a microprogram from one functional specification, and it is not possible to select the optimal logical configuration by comparing processing speed, amount of hardware, etc. There wasn't. When designing a digital logic device using a conventional automatic design device, as shown in FIG. 16, functional specifications for logic circuit synthesis and microprogram synthesis are described respectively (steps 161 and 162). After inputting them into an automatic design device and creating a logic circuit and microprogram from them (steps 163 and 164), it is necessary to compare processing speed, amount of hardware, etc. (step 165), and select the optimal logic configuration. (step 166). The purpose of the present invention is to solve these conventional problems, and to compare the performance of logic circuits based on hardwired logic or microprograms in a short time. Alternatively, it is an object of the present invention to provide an automated method for lower-level development that can select an optimal configuration by mixing image configurations. [Means for solving the problem] In order to achieve the above purpose, the lower-level deployment automation method of this g@mei inputs a combination of logical device functions and logical configuration specifications as functional specifications, and is temporarily stored in a file, and based on the specification of the function of the logic device stored in the file, a logic gate level logic circuit is created by a logic synthesis program, and a logic circuit at the logic gate level is created based on the specification of the function of the logic device. Creates a bit pattern level microprogram using , based on the specification of the logic configuration of the logic device stored in the file, switches between the logic synthesis program and the microprogram compiler to create a lower level logic circuit from the functional specifications. The feature is that the logic circuit and microprogram are selected and created by specifying the logic configuration. [Function] In the present invention, when creating a logic circuit at the logic gate level and a microprogram at the bit pattern level from the functional specifications of a digital logic device, the functions of the logic device and the designation of the logic configuration are combined as the functional specifications. input, and create a logic circuit at the logic gate level from specifying the functions of the logic device using a logic synthesis program.
A microprogram compiler creates a bit pattern level microprogram from the same function specification, and a switch to switch between the logic synthesis program and the microprogram compiler is used to create a lower level logic circuit from the functional specification based on the logic configuration specification. At this time, a logic circuit and a microprogram are selected and created from one type of function specification based on the logic configuration specification. As a result, when synthesizing a logic device whose constituent elements are lower-level logic circuits and microprograms from the corresponding functional specifications, it is possible to create the logical configuration of the logic circuit and microprogram image configuration method from one functional specification. By comparing the processing speed and amount of hardware, it is possible to select the optimal logical configuration.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a state transition input device and a screen candle representing a functional specification according to an embodiment of the present invention. The input devices include a functional specification description window 13 on the display lO, a mouse 15 for instructing m-production, and a mouse 1.
It consists of a cursor 17 that moves in conjunction with 5 and a keyboard 14 for inputting numerical information. The functional specification description window 13 is for describing state transitions representing functional specifications. This state transition is similar to the conventional one, with the state transition "r start" and "r end J"
and a description that specifies the r state 1. in which the control operations executed by the logical device are divided into fixed time units. State 2, ... state n
Description of one state mJ and “transition” representing the progress of control operation
In this embodiment, in addition to this, there is an element different from the conventional one, that is, an r#I structure that specifies the logical configuration of the state transition of interest. Drawing management information 16 consisting of a designation J and a "drawing string" for handling state transitions as a unit of description is also a component of the specification description. Note that, as in the past, the description of "state 11J" is composed of r state name 1, which is the identification name of the state, and "control action" to be executed within the state. However, the difference from the conventional method is that configuration can be specified for each control operation. Specifically, the configuration designation includes the designation of wiring logic (hereinafter represented by the symbol W) that configures the function of interest by a combination of logic circuits;
This is either a designation made up of a microprogram (hereinafter represented by the symbol m) or a designation made up of a mixture of wiring logic and a microprogram (hereinafter represented by the symbol X). In Figure 1, [
W], and [m) during the control operation of the state with the state name STm.
are examples of configuration specifications. The operation menu window 11 displays various operation commands for describing the above state transition on the functional specification description window 13. This operation command includes a ``r add'' command that places graphical symbols (corresponding to parts l, . . . n on the menu) representing the start, end, state, etc. of state transition on the functional specification description window 13; A "delete" command removes the above diagram symbol from the functional specification description window 13, a "write" command stores the symbolized state transition in a function description storage device (file), and a component 1 specifies the diagram symbol to be operated. ... Consists of part n. When performing operations using the operation menu, the cursor 17 linked to the mouse 15 is used. For example, after specifying the menu position of the "Add" command with the cursor 17, and finally the functional specification description window 1.
By specifying an arbitrary position on 3, a graphical symbol corresponding to part 1 is placed on functional specification description window 13. Text symbols such as control actions can be entered using the keyboard. FIG. 2 is a diagram showing a data structure for storing the state transition shown in FIG. 1 in a function description storage device. As shown in the second rgJ(A), the data structure of the present invention, compared to the conventional data structure, has a new data structure that handles state transitions specified by drawing threads as one group. In other words, the data structure of the present invention consists of "r configuration designation that specifies the logical configuration of a group of state transitions" and "drawing thread j and a plurality of r description elements" that are identification names of this state transition. configured. FIG. 2(B) shows details of one description element. This is composed of the same type of descriptive text as in the past, and a descriptive text that specifies a logical configuration for each control operation, unlike the conventional type. FIG. 2(C) shows details of the descriptive text when the descriptive text type is T. This is the same as before. Second
Figure (D) shows details of the descriptive text when the descriptive text type is S. This descriptive text is composed of a state name, multiple operation specifications, and multiple transition specifications. The specification of an operation consists of one control operation and the specification of a logical configuration for realizing it. FIG. 3 is a hardware configuration diagram of an automatic design device for digital logic devices showing one embodiment of the present invention. This automatic design device uses functional specifications expressed by state transitions of data structures as shown in FIG.
Or, synthesize a logic circuit whose components are microprograms at the bit pattern level. In FIG. 3, the functional description storage device 31 is the 21st! I
The logical level description storage device 33 is a file that stores the mechanical specifications of a logical device represented by the state transition of a data structure as shown in FIG. A file that stores a description of a digital logic device consisting of a microprogram at the circuit or bit pattern level. The description input device 34 is composed of a display lO having a functional specification description window 13 and an operation menu window 11 shown in FIG. It is. Also,
The main storage device 35 stores programs necessary for the processing of the CPU 30, such as reading a functional specification description stored in the functional description storage device 31 from the description input device 34, and a lower level logic gate level synthesized from the functional specifications. A read/write program 36 that stores a logic circuit or bit pattern level microprogram description in the logic level description storage device 33, a logic synthesis processing program 39 that synthesizes a logic gate level logic circuit from its functional specifications, and a bit pattern level logic circuit a microprogram compiler 38 that synthesizes a microprogram, and a logic synthesis processing program 39 and a microprogram compiler 3 according to configuration specifications described as part of the functional specifications.
A composition control program 37 for controlling which of 8 to be used is stored therein. FIG. 4 is a functional block diagram of the synthesis control program in the present invention. The synthesis control program, which is a characteristic program of the present invention, is a description that refers to the configuration specification of a given functional description and divides the description into wiring logic specification and microprogram specification. It consists of a decomposition unit 41, a synthesis activation unit 42 that activates a logic synthesis processing program 39 and a microprogram compiler 38 for each decomposed description unit to create a lower level logic circuit, wiring logic, and a microprogram. Description integration ts43 that completes the logic circuit by making connections between the logic circuits to be created, and these three
Execution control unit 44 that controls the execution of the three processing units 41 to 43
It consists of FIG. 5 is a flowchart showing the order of sounds to be processed by the execution control section in FIG. First, (1) the execution control unit 44 operates the description decomposition unit 41 to perform the following processing, that is, the function description storage device 3
The state transitions stored in 1 are classified into those with the configuration designation m, w, and x for each drawing thread, and those with the configuration designation of X are further classified into those with the configuration designation m, w in the control operation unit. A set of descriptions for each configuration specification is created (step 110). (ii) The execution control unit 44 activates the synthesis activation unit 42 to perform the following processing. That is, for the set of descriptions classified in the above procedure, the execution control unit 44 compares the logic circuit and the microprogram and selects one of them. When the process of selecting one is performed, that is, when the configuration designation is W, a logic circuit at the logic gate level is created using the logic synthesis processing program 39. Furthermore, for configuration designation m, a microprogram at the bit pattern level is created using the microprogram compiler 38. These creation results are stored in the intermediate information storage device 32 (step 111).
Next, the (fit) execution control unit 44 performs the following process by activating the description integration unit 43, that is, the integration of the logic circuit composed of wiring logic and the logic circuit composed of microprograms. The signal lines between them are connected to complete the logic circuit and stored in the logic level storage device 33 (step 112). Below, the detailed operation flow of the description decomposition unit 41 in step 110 is shown in FIG. 6, the data structure diagram of the synthesis activation unit 42 in step 111 is shown in FIG. 7, and the detailed operation flow of the description integration unit 43 in step 112 is shown in FIG. Each is shown in FIG. FIG. 6 is a processing flowchart of the description decomposition unit in FIG. 4. First, (1) one group of state transitions is extracted for each drawing from the set of state transitions (step 120). (n) determining the configuration specification of the retrieved state transition; When it is W, it branches to step 122, when it is m, it branches to step 124, and when it is X, it branches to step 125 (step 12
1). Next, (iii) register the retrieved state transition to create it in the logical configuration of wiring logic (step 122)
, Next, (rV) determines whether there is a set of unprocessed state transitions, and if there is an unprocessed state transition set, returns to step 120 and repeats the same process (step 123); The state transition is registered to be created in the logical configuration of the microprogram, and the process of step 123 is performed. (vi) Create one description identical to the retrieved state transition, and designate the original state transition as the first state transition and the copied state transition as the second state transition (step 125);
vfi) For the first state transition, determine the configuration designation for the control operation for each state, and if there is a vi constant,
Remove the operation specification from the corresponding state (step 126)
), and (4) for the second state transition, the configuration designation for the control action is determined for each state, and if there is one with m designation, the action designation is removed from the corresponding state, and step 123 Process. FIG. 7 is a data structure diagram of a logic circuit stored in the intermediate information storage device. FIG. 7(A) is a data structure diagram of a logic circuit created from a functional specification with a configuration designation of W. This is the identification name of the functional specification "drawing name -", "configuration specification J", "j" which means the logic circuit on the side where the signal is input, "destination resource 1", and "r" which means the logic circuit on the side where the signal is output. It is composed of multiple nets specifying pairs of source resources 1. Fig. 7(B) is a data structure diagram of a logic circuit created from a functional specification with a configuration specification of m. It is composed of a drawing name, which is a drawing name, a configuration specification J, and multiple nets.In addition, with the above configuration specification W, each net has a ``destination resource'' and r
In addition to the pair of source resources 1, a microprogram control signal is added to control the signal connection of this pair. FIG. 8 shows how the configuration designation of state correspondence is determined and the second state transition is performed in the processing of the first state transition and second state transition in FIG.
FIG. 3 is a diagram showing an aspect in which state transitions are separated into two state transitions. FIG. 8(A) shows a state transition in units of drawing names in which X is designated as the configuration designation. In this figure, a white rectangle represents a state in which W is designated as a control action, and a diagonally shaded rectangle represents a state in which m is designated as a control action. Figure 8 (B) is
In the second state transition created from FIG. 8(A),
The configuration designation for the control action is determined for each state, and the result is shown by removing the action designation of the m-designated control action. FIG. 8(C) shows the result of determining the configuration designation for the control operation for each state in the state transition shown in FIG. 8(A) and removing the operation designation of the W-designated control action. In other words, only that part is disabled. Note that the multiple rectangles in FIG. 8 represent each state of the state separation diagram shown in FIG. 1. The broken line rectangle in FIG. 8(C) indicates the state in which the m-designated state is removed and replaced with W. Here, separating state transitions with only m specification and state transitions with only W specification from state transitions in which m specification and W specification are mixed is to separate one control circuit (W specification state transition) from each state transition. This is to create one microprogram (created from one state transition specified by m). In FIG. 8, the "replaced state" is a state in which the control action in the original state is replaced with an invalid action (specifying that no control action is to be performed). FIG. 9 is a flowchart showing the processing procedure of the description integration unit in FIG. 4. First, (i) it is determined whether or not both a logic circuit made up of wiring logic and a logic circuit made up of microprograms are stored in the intermediate information storage device 32, and one of them is stored. If only one is stored, the process ends (step 150); (ii) If both are stored, the data structures of both are searched and all destination resources are compared with the source resource. A list of destination resources and source resources (see FIG. 10) is created in which the control signals are associated with each other (step 151). Determine whether there is a correspondence between the source resource created from the functional specification of configuration specification m and the source resource created from the functional specification of configuration specification m, and if not, terminate the process (
Step 152), (~) If there is one with the same destination, the output signals of both source resources are logically summed, and the result is connected to the input terminal of the incoming destination resource (Step 153). V) Determine whether or not there is an unprocessed item in the list. If so, return to step 152 and perform the process of determining the presence or absence of the same destination. If not, terminate the process (step 1
54). FIG. 10 is a diagram showing the processing of the description integration unit in the fourth time, and FIG. 10(A) is a diagram showing the contents of the destination resource/source resource correspondence list,
) is a connection diagram of the original logical configuration, and FIG. 10(C) is a connection diagram of the modified logical configuration. In FIG. 10(A), the destination resource DE
SI includes source resources 5RCIO and 5RC12 created from the functional specifications of configuration designation W and source resources 5RC11 created from the functional specifications of configuration designation m (the control signal is CTL).
I) is associated. In addition, the destination resource DES2 has a configuration specification m
A source resource 5RC20 (control signal CTL2) created from the functional specifications of is associated. In addition, the destination resource DES3 has a configuration specification W
A source resource 5RC30 created from the functional specifications of is associated with the source resource 5RC30. 101st! I(B) shows the original logical configuration for the destination resource DESI in FIG.
It is connected to CIO and 5RC12 via two OR circuits. On the other hand, the same DESI is connected from the functional specification of the configuration designation m to the output terminal of the source resource 5RCII and the control signal CTLI via an AND circuit. FIG. 10(C) is a logical configuration diagram obtained by modifying the connection diagram of FIG. 10(B) in the process of step 153 of FIG. 9 and integrating the connection diagram. In order to integrate the same destination resource, the source resource of the image configuration method is connected to DESl via an OR circuit before the input terminal of DESI. In this way, in this embodiment, when synthesizing a logic device having lower-level logic circuits and microprograms from functional specifications, the logic of the image configuration method of logic circuits and microprograms is synthesized from one functional specification. Since the configurations are created, it is possible to compare the processing speed, amount of hardware, etc., and select the optimal logical configuration. [Effects of the Invention] As explained above, according to the present invention, it is possible to describe the function specifications and the configuration specifications of the digital logic device as the functional specifications of the digital logic device, and these can be used to describe the same function. It is possible to create a logic circuit based on wiring logic, a logic circuit based on microprograms, or a mixture of image configuration methods.
By comparing the performance of logic circuits of the l1i configuration method in a short time, it is possible to select the optimal configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram of a functional specification state transition input device showing an embodiment of the present invention, FIG. 2 is a data structure diagram for storing the state transition of FIG. 1 in a functional description storage device, and FIG. 31! I is a hardware configuration diagram of an automatic design device for a digital logic device showing an embodiment of the present invention, No. 41! lI is a functional block diagram of the synthesis control program in FIG. 3, FIG. 5 is a flowchart showing the processing procedure of the execution control section of the synthesis control program in FIG. 4, and FIG. 6 is a procedure of the description decomposition section of the synthesis control program. FIG. 7 is a data structure diagram of a logic circuit stored in the intermediate information storage device of the present invention, and FIG. 8 is a flowchart showing how the description decomposition section of the synthesis control program shown in FIG. 4 determines the configuration designation corresponding to the state. FIG. 9 is a flowchart showing the processing procedure of the description integration section of the synthesis control program in FIG. 4, and FIG. FIG. 11 is a diagram showing an example of describing a conventional functional specification using state transitions. FIG. 12 is a diagram of a conventional data structure for storing the description in FIG. The figure shows the connection configuration of a logic circuit group synthesized from the functional specifications in Figure 11. Figure 14 is a hardware configuration diagram of a conventional automatic design device for digital logic devices.
511 is a flowchart showing the procedure for designing a digital logic device using the automatic design device shown in FIG. 14, and FIG. 16 is a flowchart showing the procedure for designing a digital logic device using the conventional automatic design device. lO: Display, 11: Operation menu window,
13: Functional specification window, 14: Keyboard, 1
5: Mouse, 16: Drawing management information, 17: Cursor, 3
0: CPU, 31: Functional description storage device, 32: Intermediate information storage device, 33: Logical level description storage device, 34: Description input device, 35: Main memory storage device, 36: Read/write program, 37: Synthesis control program, 382 Microprogram compiler, 39: Logic synthesis processing program, 41
: Description decomposition unit, 42: Synthesis activation unit, 43: Description diagram integration unit, 44: Execution control unit. Figure 4 Figure 8 Figure (Part 2) (Bl Figure (Part 1) (4) Figure (Part 3) (0 Figure 1 (Part 2) (Bl 1 J Figure (Part 1) Figure 1 Figure 1

Claims (1)

[Claims] (1) In the lower level deployment automation method that creates logic circuits whose components are lower logic gate level logic circuits and bit pattern level microprograms from the functional specifications of digital logic devices, the logic device Enter a combination of functions and logical configuration specifications, temporarily store the entered information in a file,
Based on the specification of the function of the logic device stored in the file, a logic gate level logic circuit is created by a logic synthesis program, and a bit pattern level microprogram is created by a microprogram compiler based on the specification of the function of the logic device. When creating a lower-level logic circuit from the functional specifications by switching and operating the logic synthesis program and microprogram compiler based on the designation of the logical configuration of the logic device stored in the file, A low-level deployment automation method characterized by selecting and creating a logic circuit and a microprogram based on the specification of the logic configuration.