JPH03183295A - Emphasis/de-emphasis circuit for chroma signal - Google Patents

Abstract

PURPOSE:To reduce a noise mixed in a chroma signal by providing a compensation circuit to compensate the deviation of de-emphasis characteristic from the reverse characteristic of desired emphasis characteristic with a time constant circuit comprising of the collector floating capacitor and the collector load resistor of a transistor. CONSTITUTION:Since an AC current with negative phase and in proportion to a signal flows on the collector of the transistor Q10, and a one-lap circuit consisting of an L1 and a C3 having a common point at a chroma carrier frequency Fsc(around 3.58MHz in N.TSC, and around 4.43MHz in PAL) is connected to a resistor R10 via a capacitor Co large in capacity, only the sideband component of the chroma signal is generated. Also, the maximum level at a pin 10 is limited by a limiting function with diodes D1 and D2. A voltage at the pin 10 is introduced to the positive input side of a subtractor 6, and a primary signal is subtracted, then, an emphasized chroma signal can be obtained at an output terminal 2. Therefore, since a signal from the pin 10 to the subtraction circuit 6 is remarkably small for the primary signal when a large input signal is inputted in spite of a frequency, flat characteristic can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a chroma signal recording and reproducing method, and is suitable for reducing noise mixed in chroma signals, is convenient for both recording and reproducing, and has good ejection reproducibility. This paper relates to emphasis circuits and de-emphasis circuits for Narioma signals.

[Background of the invention]

Conventional VTR technology includes the Philips V-2000 system that improves racking performance, and audio enhancement technology that performs FM modulation of audio signals and frequency multiplexing recording with low frequency converted chroma signals. .

In these techniques, the pilot signal for tracking is the band immediately below the low-pass converted chroma signal,
The FM audio signal is a signal in the "A" range just above the low-frequency conversion chroma signal.In order to obtain practical tracking performance and good audio, the FM audio signal and FM audio signal must be adjusted to a certain level. It is necessary to record at the level, but at this time,
These signals 3 are reproduced as sidebands of the low frequency chroma signal and cause deterioration of chroma image quality.

Furthermore, with regard to the random noise generated in the Tape Hen 1 system, there was no method to reduce it in the recycled thread of the VTR, which also deteriorated the chroma image quality.

[Purpose of the invention]

The purpose of the present invention is to eliminate the drawbacks of the prior art, to reduce noise mixed in chroma signals, to be convenient for both recording and reproduction, and to provide good reproducibility (no. 6). The purpose is to propose O1i.

[Summary of the invention]

In order to achieve the above purpose, @paths are provided to dynamically emphasize and suppress the sidebands of the chroma signal during recording and playback, respectively, so that the sideband components emphasized during recording are suppressed during playback, and noise components are also suppressed. .

The circuit is composed of a variable impedance element in which diodes are connected in parallel with opposite polarities, a trap circuit consisting of L and C, and other switch circuits and amplifier circuits to obtain appropriate emphasis and de-emphasis characteristics.

In addition, since both circuits for sideband 4jatA and suppression have opposite characteristics, de-emphasis characteristics are obtained by a feedback circuit configuration, which allows both circuits to be used in common and improves signal reproducibility.

[Embodiments of the invention]

An embodiment of the present invention will be explained with reference to FIG. In FIG. 1, 1 is the given terminal of the emphasis circuit, 2 is the output terminal of the emphasis@path, 3 is the input terminal of the de-emphasis circuit, 4 is the output terminal of the de-emphasis circuit, 5 is the switch circuit, 6 is the subtraction circuit, 7 is a nonlinear trap circuit, 8,
9.10 are the 1st. Second. Pins for the third integrated circuit, Q1 to Qt4 are 1 to transistors, R□ to R engineering,
is resistance, D□.

D2 is a diode, C1 and ˜C1 are capacitors, Ll and L are inductances, and J and ˜J are current sources.

The operation as an emphasis circuit during J2 recording will be explained. For example, input 0.5V p -P to the input terminal l.
A chroma signal designated as B is supplied. Next, this chroma signal is supplied from the d side of the switch circuit 5 to the base of the transistor Q8, and is led to the negative input side of the subtraction circuit 6 through the emitter of the transistor Q, and is also supplied to the base and emitter of the resistor R, and the base and emitter of the transistor Q9. and the differential pair transistor Q□. , Q1□ is opened. The capacitor C2 should be a sufficiently large capacitor, and the resistor R3 and capacitor C□ attenuate the chroma signal to create a reference DC potential, which is led to the base and emitter of the transistor Q1□, and is connected to the differential pair transistor Q1゜gQ.
Fix the other side of xl to the reference potential. Although the capacitor C2 is attached externally to the pin, it is also possible to use a capacitor inside the IC.

Transistor Q□. An alternating current proportional to the signal flows in the collector with an opposite phase, and a resistor R□ responds to this.

A voltage is generated across the resistor R10, and the chroma carrier frequency fsc (approximately 3.58 MHz for N・TSC, approximately 4.43 MHz for PAL) is applied to the resistor R10 through a large capacitor C.
Since a single wrap circuit of Ll, C, having a resonance point is connected to MH2), only sideband components of the chroma signal are generated. Also, the maximum level at pin lO is diode D
1. D. It is limited by the Nyoro limit effect.

The voltage generated at pin 10 is introduced to the positive input side of subtracter 6 to subtract the vX signal, and an emphasized chroma signal is obtained at output terminal 2. Therefore, when the input signal is large, pin I
Since the signal from O to the subtractor N6 is smaller than the original signal regardless of the frequency, the frequency characteristic of the emphasis circuit becomes a flat characteristic as indicated by O dB in FIG. On the other hand, when the six force signal The curve will look like the one shown. Moreover, when the input signal is in the middle of this range, the characteristic will be in the middle as shown in FIG. 2 at -10 dB.

The characteristics in Figure 2 are, for example, resistance R,,=R,3=120Ω
.

Resistance R work. =680Ω, inductance L1=110μ
H.

Resistance R1, = 300Ω, resistance Rti = looΩ, resistance R
Select a value such as 1,=300Ω, and connect the diode D,
,D.

This is possible if we use a Schottky diode.

Of course, the amplifier circuit consisting of transistors Q8-Q12 has a collector stray capacitance of transistor QIO and a resistor to,
Since it has a frequency characteristic mainly determined by the time constant circuit consisting of 11, the second
The resonant frequency of the nonlinear trap 7 is set so that the trap frequency shown in the figure accurately matches the gloma carrier frequency Esc. For this reason, the resonant frequency of the nonlinear trap 7 itself is usually set to a value slightly deviated from the frequency fsc. Also, choose a value near +00Ω for resistor R□, and transistor Q. It is also possible to output the collector voltage of , and use this directly as the output of the emphasis circuit.

This is a transistor Q, which is proportional to the human input signal. This is because the voltage determined by the product of the collector current of R4 and the resistor R4 is added to the voltage appearing at pin 10.

Next, the operation of the de-emphasis circuit during reproduction will be explained. For example, input 0.5Vp-P to input terminal 3.
dB to derive the emphasized chroma signal. This signal is added to the signal at pin 10 described above in an adder circuit consisting of transistor Q, Q2° resistors R1 and R. For example, if resistor I R1 = R, = R, then the signal after addition is multiplied by 2R'' and guided to the base of transistor Q3. The amount attenuated by the differential pair of Q and the lead addition is added to one helang transistor QSIQ&+resistor R5,R
,,R,, is amplified by a differential amplifier composed of a current source J4. The capacitor C is originally a capacitor that attenuates the signal in order to create a reference DC potential, but in reality, the value is chosen small so that the cutoff frequency of R, C, is between L MHz Hz and several MHz.
It is better to set it to Hz. The reason for this will be explained later. The amplified signal Z is now obtained from the collector of transistor Q through the emitter follower of transistor Q7.

This signal is the de-emphasis circuit output, and the signal at the collector of transistor Q6 is also led to the base of transistor Q11 through the b side of switch circuit 5. This produces a maximum level limited sideband signal at pin 10, as previously explained, which is in antiphase with the base signal of transistor Q. This signal is routed to the base of transistor Q2 and summed with the de-emphasis input signal. Therefore, this addition is equivalent to subtracting the sideband signal from the input signal, and sideband noise components are suppressed.

When the de-emphasis input signal is large, pin 10
Since the signal generated in the de-emphasis circuit can be considered to be small with respect to the input regardless of the frequency, the frequency characteristic of the de-emphasis circuit becomes a flat characteristic as indicated by Ode in FIG. On the other hand, when the input signal is small, the distortion generated at pin lO becomes larger relative to the original signal as the frequency moves away from Esc, and the frequency characteristics of the de-emphasis circuit are as shown in Figure 3 -20 dB. It becomes a curve. Also, when the input signal is in the middle, it is 10 in Figure 3.
It has intermediate characteristics as shown in dB.

The characteristics shown in FIG. 3 can be realized using constants as explained in the recording section. This is because the emphasis circuit and de-emphasis circuit have completely opposite circuit configurations. In other words, the configuration of the emphasis circuit is such that the original signal U and the sideband signal whose maximum level has been limited are added together, and the configuration of the de-emphasis circuit is such that the sideband signal whose maximum level has been limited is added from the de-emphasis output signal B. Create 8. and subtract it from the original signal to obtain the output signal.
This is because it is closed.

Furthermore, if the nonlinear trap circuit 7 is used for both recording and reproduction in this way, the inverse characteristics of emphasis and de-emphasis can be realized with less variation.

Since the de-emphasis circuit configuration is of the feedback type as described above, phase rotation caused by the feedback loop poses a problem. That is, a time constant circuit consisting of the collector stray capacitance of the transistor Q6 and the resistor 7 causes a phase delay in the transmitted signal, and this appears as a shift in fO in the de-emphasis characteristic as shown in Fig. 4. In terms of signal reproducibility, this is a phenomenon in which extra transients remain at the trailing edge of the chroma line.

To correct this, it is necessary to insert an appropriate circuit so that a phase lead occurs in the feedback loop, but in the embodiment shown in Fig. 1, this can be done by selecting the value of the capacitance C to a small value as described above. Become. this is.

This is because a phase delay signal caused by the resistor R1 and the capacitor icm is applied to the negative input side of the differential amplifier formed by the differential pair of transistors Q, , Q, so that a phase lead occurs in the output.

Although the capacitor C□ is externally connected to pin 8, it is also possible to use a capacitor inside the IC. However, it is better to suppress the variation in the values of resistance R4° and capacitance C□ to be smaller than usual. This is to reduce fo variation after correction.

In addition, to correct the fO deviation of the de-emphasis characteristic, the fifth
It is also possible to use a nonlinear trap circuit as shown in the figure instead of the nonlinear trap circuit 7 in FIG. In Figure 5, L□ is inductance, C1□ is capacitance,
0211 Qzz is a transistor. Transistor Q during recording. The base of is set to "Low" and a trap of inductance L1 and capacitance C3 is used. On the other hand, during playback, the frequency f s c+ (f s c
-fO), the capacitor C has a resonance point, and the inductance L
A trap consisting of 1□ is used. This corrects the fO deviation of the de-emphasis circuit.

Similarly, the fo shift of the de-emphasis circuit is shown in Figure 6.
This can be corrected by using the nonlinear trap circuits shown in FIGS. 7, 8, 9, 10, and 11. Figure 6, Figure 7, Figure 8, Figure 9, Figure 10
In the figures and FIG. 11, the same reference numerals 6-1 as in the previous figures indicate the same components, and co.

C41, C4j, C, is the capacity, L311LS11L
? lt L72 is an inductance. In Fig. 6, the resonant frequency of the inductance L and the capacitance C2 is fs c+(fs c-fo) with offset 1~ on the upper side.
transistor Q only when recording. The base of “Low”
” Set the base of transistor Q21 to “Low” only during playback.
shall be. In Fig. 7, inductance L, □ and capacitance C
Offset the resonant frequency of the resonant circuit consisting of 3 to the upper side.
The base of the transistor Q2Z is set to "Low" only during recording, and the base of the transistor Q21 is set to "Low" only during reproduction. In Fig. 8, inductance L and two capacitances c
4, the resonant frequency of the resonant circuit composed of +442 is f
sc, and the resonance frequencies of L□ and C4□ are offset upward to fsc+(fsc-fO). Transistor Q. The base of is set to "Low" only during recording. In Figure 9 L, L,.

L1+L,, fsc+(f
sc-f□), and the transistor Q 2 x is used only during reproduction.
The base of the transistor Q2□ is set to "11 Low". The base of the transistor Q2□ is set to "Low" only during recording.

In Figure 11, the resonance frequency of L71+L7□C1 is f
The resonance frequencies of sc, L7□, and C3 are set to f sc + (f sc - fO), which is offset upward, and the base of transistor Q21 is set to "Low" only during reproduction.

Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 1θ,
In FIG. 11, transistor Q 21 j Q 22
uses a PNP transistor, but an NPN transistor may also be used. In this case, the emitter and the inductance L of FIGS. 8 to 11 are ! E
Cs z, connect the Vce side of inductance L72 to GND
, and invert the logic during recording and reproduction and add it to the bases of transistors Q2x and Qzz.

The main purpose of using the examples of nonlinear trap circuits shown in Figures 5 to 11 explained above is to improve waveform reproducibility in the de-emphasis circuit, but you must be prepared to make some sacrifices in terms of noise suppression effect. Must be. This is because by shifting the trap frequency of the de-emphasis circuit, the degree of attenuation of the fsc component in the 1-lap decreases, and feedback subtraction is no longer performed effectively. Therefore, in the examples shown in FIGS. 5 to 11, the resonance frequency during reproduction is set to fsc, and the resonance frequency during recording is set to fO, which is offset downward, thereby sacrificing the noise suppression effect. However, it is also possible to improve waveform reproducibility. However, changing the recording characteristics must be limited to the extent that compatibility allows.

FIG. 12 shows a different embodiment of the invention from that shown in FIG. In Figure 12, number 3 is the same as the previous figure. Symbols indicate the same components, 11 is the pin for the 975 circuit in Figure 4, C'a
tc7. is a capacitance, and R17 is a resistance.

The difference between the embodiment of FIG. 12 and the embodiment of FIG. 1 is that the nonlinear trap circuit 7 is replaced by a nonlinear trap circuit including a bridge T-type trap. The operations of other parts are similar. The resonance frequency of L□, C′+C′, is f
sc, and select a resistor R11 that is four times the pure resistance numerator of the inductance L. At this time, the signal generated at pin 11 has a much smaller fsc component than the signal generated at pin 10 in FIG. This is the 1st V! In the embodiment U, since the inductance L0 is a pure resistance, the trap consisting of the inductance L and the capacitance CJ cannot have a very deep attenuation, whereas in this embodiment, the inductance L1 is a pure resistance and the resistor R□7 is used for the pure resistance. This is because they work to cancel each other out, resulting in a very deep attenuation (-40 to -50 dB).

That is, when a signal as shown in FIG. 13A is input to input terminal 1 or 3, the waveform generated at pin 10 in FIG. 1 is as shown in FIG. 13B. It will look like Figure C. When the input waveform is contaminated with random noise or other disturbances, the embodiment of FIG.
The waveform becomes as shown in Figure 13, and since the interference component is attenuated by the limiting effect, the interference component subtracted from the original signal by the de-emphasis circuit becomes smaller and the interference is not suppressed much. Therefore, in order to increase the noise regulation effect in the embodiment of FIG. 1, it is necessary to make the pure resistance of L□ sufficiently small, and using an expensive inductance is not necessarily cost effective.

In contrast, in this embodiment, the waveform of pin 11 becomes as shown in FIG. 13E without the interference component being subjected to the limiting effect.
The de-emphasis circuit effectively subtracts the interference component and suppresses the noise component well.

In this example, a phase shift occurs in the de-emphasis circuit,
If the waveform reproducibility is not good, it can be corrected by using an inductance circuit with a changeover switch of the type shown in FIGS. 7, 9, and 11 in place of the trap L4. In this case, the noise suppression effect is better than when the fO deviation is corrected using a similar method in the embodiment of FIG.

The bridge T-type trap used in this embodiment is not limited to the example shown in FIG. 12, and various three-end notch filters can also be used.

Although the embodiments shown in FIGS. 1 and 12 have been described using a recording/reproducing circuit, separate circuits may be used for emphasis and de-emphasis. Furthermore, in the same embodiment, the chroma signal was explained in the fsc (approximately 3.58 MIIz for NTSC, approximately 4.43M II z for PAL) band.
The present invention is not limited thereto, and is effective even when configured to process signals in the chroma signal recording frequency band of a VTR, for example, 740KIIz.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the noise mixed in the chroma m number, which is effective in improving the chroma S/H of the reproduced image.

Further, the signal reproducibility of the emphasis circuit and the de-emphasis circuit is good, and it is easy to combine both circuits so as not to increase the size of one circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the emphasis circuit/de-emphasis circuit according to the present invention, FIG. 2 is a characteristic diagram showing an example of the emphasis characteristics of the present invention, and FIG. 3 is a de-emphasis circuit of the present invention. Characteristic diagram showing an example of characteristics,
Fig. 4 is a characteristic diagram showing an example of the de-emphasis characteristic with deviation of fO, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9,
1 (FIGS. 1 and 11 are circuit diagrams showing examples of nonlinear trap circuits used in the present invention, and FIG. 12 is a circuit diagram showing another embodiment of a dual-purpose emphasis circuit/de-emphasis circuit according to the present invention. The circuit diagram and FIG. 13 are explanatory diagrams showing waveforms of each part of the circuit of the present invention. Explanation of the same symbols 1. Input terminal of the emphasis circuit. 2. Output terminal of the emphasis circuit. 3. De-emphasis. Input terminal of the circuit. 4. Output terminal of the de-emphasis circuit. 6. 'fIC17, circuit.

Claims (1)

[Claims] 1. A nonlinear trap circuit including a resonant circuit whose load is a diode parallel connection circuit in which diodes are connected in parallel with opposite polarities, and a sideband signal thereof by passing a recording chroma signal through the nonlinear trap circuit. a first transmission line for taking out the
a chroma emphasis circuit comprising a second transmission path for transmitting the recorded chroma signal without going through the nonlinear trap circuit, and an adder circuit for adding the outputs of the first and second transmission paths;
It consists of a third transmission line including a transistor that has a collector load resistance and amplifies the reproduced chroma signal, and a feedback path that negatively feeds back the output of the third transmission line to the input side of the third transmission line via the first transmission line. The resonant frequency of the nonlinear trap circuit is set to obtain the desired emphasis characteristic, and the de-emphasis characteristic is controlled by a time constant circuit consisting of the collector stray capacitance and collector load resistance of the transistor. 1. An emphasis/de-emphasis circuit for a chroma signal, further comprising a compensation circuit for compensating for deviation of the chroma signal from a desired emphasis characteristic. 2. The chroma signal emphasis/de-emphasis circuit according to claim 1, wherein the compensation circuit comprises another time constant circuit connected to the base of the transistor.