JPH0318372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width conversion circuit, and more particularly to a pulse width conversion circuit of a clock distribution system suitable for a data processing device.

[Prior Art] Generally, in a clock distribution system, it is necessary to specify a regulation for the pulse width of a clock, and in particular, the regulation of the pulse width becomes stricter as the clock period becomes smaller.

Conventionally, the first method of determining the clock pulse width is
Either by a leading edge differential circuit as shown in the figure or by the first
A widely known method is to create a pulse having an arbitrary pulse width by further passing an output signal differentiated by a leading edge differentiation circuit as shown in the figure through a pulse width conversion circuit shown in FIG.

That is, the conventional circuit shown in FIG. It is provided with a differential waveform generating circuit 3 which performs AND or NAND with the signal c and the input signal a to differentiate the input signal a. Further, the conventional circuit shown in FIG. 2 includes a set-reset type latch 5 which receives an input signal f as a set input, and an output signal i which delays the output signal g of the set-reset type latch 5 and uses it as a reset signal for the set-reset type latch 5. and a second delay circuit 6 for output.

FIG. 3 is a time chart showing the operation of the leading edge differentiator circuit of FIG. 1 when a normal input signal and an input signal with a narrow positive pulse width are applied, and FIG. 3 is a time chart showing the operation of the pulse width conversion circuit of FIG. 2 when an input signal with a wide pulse width is applied. In FIGS. 3 and 4, each reference numeral corresponds to each reference numeral in FIGS. 1 and 2, respectively.

In FIG. 3, the case of a normal input signal is shown by a dotted line, and the case of an input signal with a narrow positive pulse width is shown by a solid line. As shown in the time chart in Figure 3, in the case of a normal input signal, a pulse with the correct pulse width is output as the output signal d or e, but when an input signal with a narrow positive pulse width is applied, , the input signal a is not differentiated and a pulse with a narrower pulse width than the correct pulse width is output as the output signal d or e.

As shown in the time chart of FIG. 4, the dotted line indicates the case where a normal input signal is input to the pulse width conversion circuit of FIG. 2, and the solid line indicates the case where the input signal with a wide range of positive pulses is input. As the time chart in Figure 4 shows, in the case of a normal input signal, a pulse with the correct pulse width is output as the output signal g or h, but when an input signal with a wide positive pulse width is applied. In this case, a pulse with a wider pulse width than the correct pulse width is output as the output signal g or h.

If the pulse width of the input signal fluctuates and is sometimes narrower and sometimes wider than the required pulse width,
The leading edge differentiator circuit in Figure 1 and the pulse width conversion circuit in Figure 2 cannot be used alone; the output side of the leading edge differentiator circuit in Figure 1 is connected to the input side of the pulse width conversion circuit in Figure 2. The leading edge differentiating circuit shown in FIG. 1 differentiates the leading edge of the input signal, outputs a pulse with a narrower pulse width than the required pulse width, and
The pulse width conversion circuit shown in the figure uses a pulse width conversion circuit configured to widen the pulse width to the required value and output it.

In the pulse width conversion circuit that connects the circuits shown in FIG. 1 and FIG. It is necessary to set the pulse width to be wide and narrower than the required pulse width, as described in the explanation of FIG. However, as the clock period becomes smaller, the required pulse width also becomes narrower, resulting in the disadvantage that the pulse width of the output signal of the leading edge differentiator shown in FIG. 1 must be adjusted accurately over time.

[Object of the invention] The object of the present invention is to solve this drawback,
An object of the present invention is to provide a pulse width conversion circuit that facilitates setting of the pulse width of an output signal of a leading edge differentiating circuit.

[Structure of the invention]

The present invention includes a set-reset type latch, and a second delay circuit whose input side is connected to the output side of the set-reset type latch and whose output is connected to the set-reset input terminal and is capable of delaying the output signal of the set-reset type latch by an arbitrary delay time. a first delay circuit that is supplied with an input signal and delays the input signal; an inverter circuit that inverts the output signal of the first delay circuit; and a differential circuit that ANDs the output signal of the inverter circuit and the input signal. a waveform generating circuit, including a leading edge differentiator circuit for obtaining a leading edge differential waveform output of the input signal, and the leading edge differentiator circuit is connected to the output of the set-reset type latch and is connected to the output signal of the set-reset type latch and the front edge differentiator circuit for obtaining a leading edge differential waveform output of the input signal; A pulse width conversion circuit comprising a NAND circuit which outputs an output obtained by NANDing an edge waveform output and whose output is connected to a set input terminal of the set-reset type latch.

Further, in the pulse width conversion circuit, a third delay circuit for slightly delaying the input signal instead of the inverter circuit of the leading edge differentiating circuit, and an output signal of the third delay circuit and an output signal of the first delay circuit. This is a pulse width conversion circuit characterized by replacing the waveform generation circuit with an AND waveform generation circuit.

Further, the pulse width conversion circuit is characterized in that in the two circuits, a leading edge differential waveform generating circuit and a NAND circuit are integrated to form a three-input NAND circuit.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings. 5 and 7 are circuit configuration block diagrams of embodiments of the present invention. Each reference numeral in FIGS. 5 and 7 corresponds to each reference numeral in FIGS. 1 and 2, respectively.

The characteristic configuration of this embodiment is that the output signal of the set-reset type latch shown in FIG. 2 is connected to the output of the leading edge differentiating circuit shown in FIG. A circuit is provided for returning the output signal to the leading edge differentiating circuit and controlling the output signal of the leading edge differentiating circuit.

The pulse width conversion circuit of the embodiment shown in FIG. An input signal a is input to a first delay circuit 1, and the delay circuit 1 outputs an output signal b obtained by delaying the input signal a. This output signal b is input to an inverter circuit 2, which inverts the output signal b and outputs an output signal c. The input signal a and the output signal c are input to a differential waveform generation circuit 3, and the differential waveform generation circuit 3 performs an AND operation on the input signal a and the output signal c to determine the leading edge of the positive pulse of the input signal a and the output signal c. output signal c
The output signal d narrowed by the leading edge of the negative pulse of
Output.

The output signal d is input to the NAND circuit 7, and the NAND circuit 7 outputs an output signal k in which the leading edge of the positive pulse of the output signal d is made the leading edge of the negative pulse. The output signal k is input to the set-reset type latch 5, sets the set-reset type latch 5, and outputs the output signal g.
is set to "0" and the output signal h is set to "1". Output signal g
is input to the NAND circuit 7, and the output signal d
and is told. As mentioned above, the NAND circuit 7 makes the leading edge of the positive pulse of the output signal d the leading edge of the negative pulse of the output signal k, and also makes the leading edge of the negative pulse of the output signal g the leading edge of the negative pulse of the output signal k. By setting the trailing edge of the input signal d as the trailing edge, a leading edge differential waveform of the input signal d can be obtained.

The output signal g is also input to a second delay circuit 6, which delays the output signal g and outputs an output signal i. The output signal i is input to the set-reset type latch 5 and resets the set-reset type latch 5, thereby setting the output signal g to "1" and the output signal h to "0". Further, the delay time of the second delay circuit 6 is set so that the pulse width of the negative pulse of the output signal g or the positive pulse of the output signal h becomes the required pulse width.

As described above, the output signal d of the NAND circuit 7 of the leading edge differentiating circuit 8 is controlled by the output signal g of the set-reset type latch 5 to perform leading edge differentiation.
If the output signal d is narrower than the sum of each delay time and the required pulse width, the leading edge differentiation of the output signal d is performed, so it is necessary to accurately adjust the delay time of the first delay circuit 1. It disappears.

FIG. 6 shows a time chart of the embodiment of FIG. 5, where the solid line shows the case where the output signal d is narrower than the required pulse width, and the dotted line shows the case where the output signal d is wider than the required pulse width. show. Each symbol in FIG. 6 corresponds to each symbol in FIG. 5, respectively.

As shown in FIG. 6, even if the output signal d is narrower than the required pulse width (solid line) or wider than the required pulse width (broken line), the output signal g of the set-reset type latch 5 is As the NANDed output signal, the output signal k of the same pulse width is self-aligned to the pulse width of the sum of the delay times of the NAND circuit 7 and the set-reset type latch 5, and the set signal of the set-reset type latch 5 is output. The output signal of the requested pulse width can be outputted as the output signal g or output signal k, which is the output of the pulse width conversion circuit.

FIG. 7 shows a second embodiment of the invention. In FIG. 7, instead of the inverter circuit 2 in FIG. 5,
A third delay circuit 9 and a delayed waveform creation circuit 10 are newly inserted.

With this configuration, an input signal e is input to the first delay circuit 1, and the delay circuit 1 outputs an output signal b obtained by delaying the input signal a. The input signal a is also input to a third delay circuit 9, which outputs a slightly delayed output signal l. The output signal b and the output signal l are input to the delayed waveform generation circuit 10. The delay waveform creation circuit 10 outputs signals b, l.
By taking the NAND of , an output signal m narrowed by the leading edge of the positive pulse of the output signal b and the leading edge of the positive pulse of the output signal l is output. The output signal m and the input signal a are input to a differential waveform generation circuit 3, and the differential waveform generation circuit 3 ANDs the input signal a and the output signal m to determine the leading edge of the positive pulse of the input signal a and the output. The output signal d is narrowed by the leading edge of the negative pulse of the signal m. Since the explanation after the output signal d is the same as that in FIG. 5, it will be omitted. The circuit shown in FIG. 7 is particularly effective when the negative pulse width of the input signal a is narrow.

Here, the first delay circuit 1 has a delay time that makes the delay time from the input signal a to the output signal m equal to the pulse width of the required differential signal. The third delay circuit 9 has a delay time from the input signal a to the output signal g, which is smaller than the minimum pulse width of the input signal a and smaller than the delay time of the first delay circuit 1.

FIG. 8 is a time chart showing the embodiment of FIG. In FIG. 8, the solid line indicates the case where the output signal d is narrower than the required pulse width, and the dotted line indicates the case where the output signal d is wider than the required pulse width. Each symbol in FIG. 8 corresponds to each symbol in FIG. 7, respectively.

As shown in FIG. 8, even if the output signal d is narrower than the required pulse width (solid line) or wider than the required pulse width (dashed line), the output signal g of the set-reset type latch 5 remains unchanged. In order to output the set signal of the set-reset type latch 5, the output signal k with the same pulse width is self-aligned to the pulse width of the sum of the delay times of the NAND circuit 7 and the set-reset type latch 5 as a NANDed output signal. An output signal having a normal required pulse width can be outputted as an output signal g or an output signal k, which is the output of the pulse width conversion circuit.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which the leading edge differentiating circuit represented by FIG. 1 is connected to the pulse width generating circuit shown in FIG. 2, and the output signal of the leading edge differentiating circuit is By controlling the signal, the output pulse width of the leading edge differentiating circuit can be easily adjusted.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of the conventional system, Figures 3 and 4 are waveform diagrams of various parts of the system shown in Figures 1 and 2, and Figures 5 and 7 are of the embodiment of the present invention. The block diagrams, FIGS. 6 and 8, are waveform diagrams of various parts of those shown in FIGS. 5 and 7. DESCRIPTION OF SYMBOLS 1...First delay circuit, 2...Inverter circuit, 3...Differential waveform creation circuit, 5...Set-reset type latch, 6...Second delay circuit, 7...NAND gate, 8...Leading edge differential Circuit, 9...Third delay circuit, 10...Delayed waveform creation circuit.

Claims (1)

[Scope of Claims] 1. A set-reset type latch, the input side of which is connected to the output side of the set-reset type latch, and the output side connected to the reset input terminal of the set-reset type latch, so that the output signal of the set-reset type latch can be delayed for an arbitrary delay time. a second delay circuit that can delay the input signal; a first delay circuit that is supplied with an input signal and delays the input signal; an inverter circuit that inverts the output signal of the first delay circuit; The leading edge differentiating circuit has a differential waveform creation circuit that ANDs an input signal and obtains a leading edge differential waveform output of the input signal, and the leading edge differentiating circuit combines the output signal of the set-reset type latch and the leading edge differential waveform. 1. A pulse width conversion circuit comprising: a NAND circuit which outputs an output obtained by NANDing the output of the pulse width converter and the output of the set reset type latch. 2. A third delay circuit that slightly delays the input signal instead of the inverter circuit in the leading edge differentiating circuit, and creating a delay waveform by NANDing the output signal of the first delay circuit and the second delay signal. The pulse width conversion circuit according to claim 1, further comprising a circuit.