JPH03184150A - information transfer device - Google Patents

Abstract

PURPOSE:To obtain a buffer controller having a simple constitution by providing a buffer memory, an attribute buffer memory, and a decision control means to interpret the attribute and to decide the treatment of the information on the buffer memory. CONSTITUTION:When the transfer of data is desired to the CPU side from the I/O devices 6 and 7, a transfer request signal and the transfer data are sent to the I/O data and a transfer bus of each of both devices 6 and 7. The processing (b) is carried out in a step 1. A multiplexer MPX 5 gives the priority to a request to return an I/O data transfer acknowledge signal 16 and at the same time saves the data received from the bus 15 into a latch 5a. Then the data are written into a data storing field 4 and an identification field 3 of a FIFO memory device 2 via an MPX bus 9 based on the pointer information on a FIFO controller 1 with the value of the I/O data (name) A, for example, used as the identification data 10. Then the processing (c) is carried out in a step 2 and when a data bus 11 is not used yet. Thus the transfer of data is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer control device for transmitting information between a processing device and a peripheral device.

[Prior Art] In a conventional data processing device, when connecting a large number of input/output devices that have high processing power on the CPU side and are relatively slow in speed, it is necessary to compensate for the difference between the processing speed on the CPU side and the processing speed on the I10 side. Therefore, a buffer device is sometimes provided between the CPU side and the I10 side.

[Problems to be Solved by the Invention] In the conventional system, a buffer control device only allows one I10 connection as its connection target, that is, only one connection in a facing manner. This resulted in a large cost increase.

[Means for Solving the Problems (and Effects)] According to the present invention, in a system for transmitting information between an information processing device and a peripheral device, a system for transmitting information between the information processing device and the peripheral device; a buffer memory that stores information to be
An attribute buffer memory for storing attribute information of information stored in the buffer memory, and a decision control means for interpreting the attribute information stored in the attribute buffer memory and determining how to handle the information in the buffer memory. This makes it possible to realize a buffer control device that can perform buffer control with a simple configuration.

[Embodiment] FIG. 1 shows a buffer control device of the present invention. In the figure, l is the FIFO control device that controls the entire FIFO buffer mechanism, and the write pointer PTI, t
It has an i pointer PT2. 2 is a FIFO memory device that constitutes the FIFO itself, and has an I10 identification field 3 for storing data representing an I10 device and a data storage field 4 for storing data.

5 is an I10 multiplexer that switches and transfers data from each Ilo;
Transfer 10 data. 6 is I10 device A, 7 is I10
Device B, 8 is an I10 identification decoder for identifying I10 devices, 9 is a multiplexer data bus, 10 is an I10
11 is a CPU side data bus; 12 is a signal line that sends I10 identification read data; 13 is a signal line that sends identification data;
is the signal line that sends the I10 device A-DMA request signal,
14 is a signal line that sends a DMA accrual signal, 15 is I1
0 data transfer bus, 16 is a signal line for sending an I10 data transfer acknowledge signal, 17 is a signal line for sending an I10 side FIFO write pointer, and 18 is a signal line for sending a system side FIFO 9 output pointer. 19 is a signal line for sending a write request signal, and 20 is a signal line for sending a read request signal.

In the above configuration, I, which is a component of the data processing device,
10 device A/6 or I10 device B/7 sends data to C.
The case where it is desired to transfer to the PU side will be described with reference to FIG. First, the I10 data held by each I10 device and a transfer request signal and transfer data are sent to the transfer bus 15. At the First in step in FIG. 2a, processing as shown in FIG. 2 is performed. The I10 multiplexer 5, which constantly monitors the I10 data transfer path 15, gives priority to transfer requests from the I10 data transfer bus 15, and
10 device B.7, the I10 data transfer acknowledge signal 16 is returned, and data (I10 data, transfer data) is saved in the latch 5a from the selected I10 data transfer path 15. Thereafter, the FIFO control device 1 monitors the usage status of the FIFO memory device 2 using the pointer PTI, and if there is space, moves the write pointer on the I10 side to the corresponding memory location. After this, I
10 multiplexer 5 passes the data saved for transfer through multiplexer bus 9 and to I1
I10 on the side that returned the 0 data transfer acknowledge signal 16
Data (name) For example, in this example, I10 device A.
The value of "A" corresponding to 6 is written as I10 identification data 10 to data storage field 4 and I10 identification field 3 in FIFO memory device 2 based on the pointer information of FIFO control device 1, respectively. After this, when the First out step is performed, the CPU
If the side data bus 11 is not in use, the FIF
The OIIIm device 1 addresses the system side read pointer to the corresponding FIFO memory device 2 as shown in FIG. 2C.

The addressed data storage field 4 and I10 identification field are each controlled by the FIFO control circuit 1 and read out as the CPU side data bus 11 and I10 identification read data 12, respectively. The signal read as the I10 identification read data 12 is input to the I10 identification decoder 8, and for example, the I10 identification read data 12 is 'A'.
If so, the decoded result is I10 device A-
A DMA request signal 13 is generated. This DMA request signal is used together with the DMA acknowledge signal 14, and is used as a handshake signal when using the CPU side data bus 11.

[Other Embodiments] This embodiment has been described assuming that two I10 devices are connected to the buffer mechanism, but depending on the configuration of the I10 multiplexer 5, the maximum number of I10 devices may be connected. Furthermore, the field width of the I10 identification field 3 and data storage field 4 that constitute the FIFO memory device 2 is arbitrary and there is no restriction.Other fields such as a parity field may be any field necessary for the system. may be provided.

In the above example, the functions of the MPX 5 and the decoder 8, that is, the data written to the identification field may be generated and interpreted by the peripheral device and the CPU, respectively.

[Effects of the Invention] By adopting the above method, it has become possible to use one FIFO buffer mechanism as a buffer compatible with a plurality of 110 devices. The economic effects of this are very large.

Also, regarding the CPU side interface, the conventional D
MA ink can be inherited and used without changing the face.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a buffer control device embodying the present invention. FIG. 2 a, b, and c are flowcharts showing an outline of control operations. FIG. 1 is a FIFO control device, 2 is a FIFO memory device, 3 is an I10 identification field, 4 is a data storage field, 5
is I10 multiplexer, 6 is I10 device A, 7 is I1
0 device B, 8 is I10 identification decoder diagram FIFI7/~7A fi Hatake 810

Claims (3)

[Claims] (1) A system for transmitting information between an information processing device and a peripheral device, comprising: a buffer memory that stores information transmitted between the information processing device and the peripheral device; and a buffer memory that stores information transmitted between the information processing device and the peripheral device; An information transfer device comprising: an attribute buffer memory that stores attribute information of information stored in the attribute buffer memory; and a decision control unit that interprets the attribute information stored in the attribute buffer memory and determines how to handle the information in the buffer memory. (2) The information transfer device according to claim 1, wherein the decision control means is included in the information processing means. (3) The information transfer device according to claim 1, wherein means for writing attribute information into the attribute buffer memory is provided in the peripheral device.