JPH03185725A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve etching accuracy by monitoring current flowing in a semiconductor and an etchant at the time of etching using such an etchant that etches the semiconductor only when light is radiated and determining an etching amount of the semiconductor based on a change in the current value. CONSTITUTION:An etchant 10 which etches a semiconductor only when light is radiated is use, and the etching amount is sensed by current flowing between the semiconductor 9 and the etchant 10. Since the current varies according to the thickness of the semiconductor under radiation of constant light, the thickness of the semiconductor can be sensed by a change in the current. Thus management of etching time is not required, fluctuation of etching caused by the irregularity of the surface state of the semiconductor 9 and etching stop is eliminated so that wet etching can be done with good accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to wet etching of semiconductors.

[Conventional technology]

Dry methods and wet methods are suitable for etching semiconductors, and the dry method is widely used because of its superior etching controllability. However, wet etching is still used for compound semiconductors such as GaAs, whose device characteristics vary greatly due to damage caused by dry etching.

Among compound semiconductor devices, those that require the highest etching precision are GaAe field effect transistors (hereinafter referred to as FK7) and high mobility field effect transistors (hereinafter referred to as HKM).
(abbreviated as T).

Hereinafter, a conventional method for manufacturing a semiconductor device will be explained with reference to the drawings, using GaAe FICT as an example.

Figure 5 is a cross-sectional view showing the structure of GaAs PET, vf,
Figure 6 shows the process of forming the concave structure shown in Figure 5.
It is a sectional view of ET. In the figure, (1) is the source [L(
2) is the drain tr, (3) is the gate electrode, (4)
is the operating layer.

(5) is a concave structure in which the operating layer (4) is removed by etching (hereinafter referred to as a recessed structure), (61 is a buffer layer,
(7) is a GaAs semi-insulating substrate, and (8) is a resist. In GaAeF'ET, in order to reduce parasitic resistance and improve reverse breakdown voltage,
Electric! ij! (13 and drain current FM (2) flit
Gate city 11ii formed in (3) Dynamic f′E of part
i/1l(4) uses recessed structure (5>).

GaABFET channel/L in recess Narazou (5)
/11' flow is the difference between the initial operating layer 11d and the etching depth t for forming the recess structure (5).
) Dynamics immediately below f): Determined by layer (4) N, a. GaA
The performance and yield of aFKT are mainly due to channel/I
/ Determined by current. In other words, accurately controlling a to a desired value with good reproducibility improves GaAs FIT (D performance and yield.The formation of a normal recess structure (5) is as shown in Fig. 6. 4)
, form the drain electrode (2), pattern the recess structure (5) with a resist (8), and etch the exposed recess structure (5) several times using a wet etchant. 1.1Th for each
1), the channel/l/current between drain W Ik (2) is measured, and a desired current value (thickness a) is determined while correcting the etching time.

[Problem to be solved by the invention]

Since the conventional semiconductor device manufacturing method is performed as described above, it is necessary to determine the etching time by experience, and even at a constant etchant composition and etching temperature.
Due to the surface condition of the active layer and variations in etching stoppage due to water washing, the φI limit is ±10+% of the desired value. That is, in order to improve the performance variation and reproducibility of GaAaPET, it is important to improve the accuracy of wet etching when forming the recess structure, and a high level of skill is required.

This invention was made to solve the above-mentioned problems, and uses an etchant that etches the semiconductor only when it is irradiated with light, and detects the amount of etching based on the current flowing between the semiconductor and the etchant. Yoshi,
The purpose is to improve the etching accuracy of semiconductors.

[Means to solve the problem]

In the semiconductor device manufacturing method according to the present invention, the amount of etching of the semiconductor can be determined by the current flowing between the semiconductor and the etchant, and etching can be stopped by cutting off light irradiation, so that the etching time can be controlled. Wet etching can be performed with high precision, eliminating the need for etching and eliminating variations in etching due to variations in the surface condition of the semiconductor and variations in etching stop.

[Effect]

In the etching of the semiconductor in this invention, the semiconductor is etched by a chemical reaction between the holes generated when the semiconductor is irradiated with light and the etchant.

f of hole! Temperature and semiconductor resistance (film thickness/carrier concentration)
The first class determined by and occurs. This current changes according to the thickness of the half-groove body under a constant amount of light irradiation, so the thickness of the half-groove body can be detected by the change in current. That is, the amount of etching can be controlled by monitoring the above-mentioned flow rate.

〔Example〕

An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings, taking GaA8PICT as an example.

Figures 1 and 4 are schematic cross-sectional views of an etching apparatus for GaAs wafers. Figure 1 shows the process of etching by light irradiation and doping profile measurement by the C-v method at the same time. Figure 4 shows the process shown in Figure 1. The following steps are shown. Second
The figure is a graph showing the relationship between the photocurrent measured in the process shown in Figure 1 and the depth from the surface of the active layer. Figure 3 is the graph showing the relationship between the carrier concentration measured in the process shown in Figure 1 and the depth from the surface of the active layer. This is a graph showing. In the figure, (9) is a GaAs wafer, Q
Otel etchant, αD-sealing, 0 is sapphire window, α3Fi force-bon am, (l small is electrode on wafer, α9 is ammeter, α61 is platinum electrode, α〃 is cell, shout is wafer holder, Tsukuda is It is light.

Next, the manufacturing method will be explained.

KOH, Tyron, and the like are known as etchants that etch GaAa only when irradiated with light. As shown in Figure 1, a part of the GaAs wafer (9) was brought into contact with the Elachan QG via the sealing (2).

GaAs wafer (9) through sapphire window bt-
A light beam with a large energy such as the bandgap energy of Ag is irradiated. At this time, a DC bias is applied between the carbon ttia in the etchant GO and the electrode α◆ on the wafer, and the current during etching is measured with an ammeter (2). At the same time, an AC bias is applied between the platinum electrode αG in the etchant α0 and the mc electrode α4 on the wafer.
The capacitance voltage (a-v) between the aAs wafer (9) and the etchant α0 is determined, and the C-V characteristic is
The relationship between the thickness of the active layer (4) on the GaAs wafer (9) and the carrier concentration (doping profile lv) is determined.

From the above measurements, it has been found that if the recess structure (5) after etching is desired to have a depth a of 100 OA, it is sufficient to apply a photocurrent, that is, to stop the irradiation of the light QIJ at point A in the figure.

Next, as shown in Fig. 3, the GaAs wafer (9) with a constant value of Etchant αO on the entire surface of GaAs wafer (9)
The GaAs wafer (9) is brought into contact with the GaAs wafer (9) and irradiated with light O9, and when the photocurrent reaches 82% of the value at the start of etching, the light a pot is stopped and the GaAs wafer (9) is washed with water to complete the etching.

The source pattern is determined by the above etching inconsistency.
(1) Drain [m (The actual measured value of the channel current for 21 wafers is ±5 mm for the entire 2-inch wafer, which can be reduced to less than half of the conventional value. In addition, in the conventional manufacturing method, the etching time setting was In contrast, the manufacturing method according to the present invention detects only the photocurrent value, whereas the manufacturing method according to the present invention detects only the photocurrent value.

Since it is only necessary to stop the photocurrent, the reproducibility can be greatly improved from the conventional ±15 scratches to ±5 scratches.

In addition, in the above example, the case of manufacturing l;i GaAs F Ie T was explained, but in addition to PET, HFiM
Needless to say, the present invention can also be applied to T and heterojunction devices. Furthermore, the half-soul material is not limited to GaAa.

Even when applied to other compound semiconductors, 81j#, the same effects as in the above embodiment can be obtained.

[Effect of explosion]

As described above, according to the present invention, the amount of etching is determined according to the change in photocurrent during etching, which reduces the conventional etching time selection error and etching error caused by the surface condition of the semiconductor wafer. Etching errors caused by stopping etching due to washing with water can be stopped simply by stopping light irradiation, so etching accuracy can be greatly improved.

[Brief explanation of drawings]

@1 Garden and Figure 4 are part 1 of the semiconductor device according to this invention! !
! FIG. 1 is a schematic cross-sectional view of an etching apparatus for GaAs wafers according to an embodiment of the manufacturing method.
Fig. 4 shows the process of performing Fi@1 constant, Fig. 2 shows the process after Fig. , the third garden shows the carrier concentration and dynamic f) measured in the process shown in wc1.
:4 Graph showing the relationship between the depths from the surface, FIG. 5 is a cross-sectional view showing the structure of a conventional IjaA117ET, and FIG. 6 is a GaAsFET showing the formation process of the recessed structure shown in FIG. 5.
FIG. In the figure, (9) is a GaAs wafer, αo#i etchant, n+1 ceiling, (2) is a sapphire window,
a3 is carbon army, bomb, Q4) is taku on wafer, (
A) is an ammeter. ut3 is platinum [koshiki, C1 force is cell, shout is wafer presser,
09 is light. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A method for manufacturing a semiconductor device, which uses an etchant that etches the semiconductor only when irradiated with light, monitors the current flowing through the semiconductor and the etchant during etching, and determines the amount of etching of the semiconductor based on changes in the current value.