JPH03185748A - Manufacture of dielectric isolation substrate - Google Patents

Abstract

PURPOSE:To restrain the warp of a substrate and to reduce a production cost by a method wherein an element formation region on a (100) Si substrate is etched anisotropically and Si is deposited by a vapor growth method. CONSTITUTION:An etching mask 1 is removed; an oxide film is formed by thermally oxidizing an anisotropically etched face; in addition, one part of the oxide film is etched, and a (100) Si substrate exposed part 5 is formed; and an isolation film 4 is formed. Then, polycrystalline Si 6 which is deposited from the upper part of the isolation film 4 by a vapor growth method is deposited. Si near the (100) Si substrate exposed part 5 which has been formed by etching one part of the isolation film 4 is transformed into deposited single- crystal Si 7. In addition, Si is grown, by a vapor growth method, on an Si substrate 2 which has been processed, and deposited single-crystal Si 7a is formed. Lastly, the deposited single-crystal Si 7a is ground and polished down to an A-A' face, and an element formation region 3a is formed. Thereby, a dielectric isolation substrate without a warp can be obtained in a short time and by using a growth gas of a small amount.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a dielectric separation substrate, and particularly to a dielectric separation method that can suppress warpage of the dielectric separation substrate and reduce manufacturing costs. The present invention relates to a method for manufacturing a substrate.

[Conventional technology]

Conventionally, this type of dielectric isolation substrate is produced by anisotropically etching a single crystal silicon substrate (hereinafter referred to as (100) Si substrate) 2 having a (100) crystal orientation, as shown in FIG. 3(a). Then, as shown in FIG. 3(b), after forming an oxide film for element isolation (hereinafter referred to as isolation film) 4, as shown in FIG. 3(C).
As shown in FIG. 3(d), several hundred μm of deposited polycrystalline silicon (hereinafter referred to as polycrystalline Si) 6 was deposited by the vapor phase growth method, and this was used as a support substrate, as shown in FIG. 3(d). <
100) DD' plane in FIG. 3(c) from the Si substrate side 2,
In an intra-film manufacturing method, the deposited polycrystalline Si 6 is removed by grinding and polishing up to the CC' plane to form an element forming region 9 of a (100) Si substrate.

[Problem to be solved by the invention]

Conventionally, a general method for manufacturing a dielectric isolation substrate is (100)
Using an oxide film or the like as a mask, the St substrate is anisotropically etched outside the element formation region to form a separation film such as an oxide film. Next, several hundred μmkv of Si is deposited on the separation ridge by a vapor phase growth method to form a support substrate.

At this time, the supporting substrate becomes polycrystalline St, but has a thickness of several hundred μm.
The disadvantage is that the deposition requires a very long time and a large amount of growth gas (eg 5iHCff13).

Furthermore, since the (100) St substrate and polycrystalline Si have different coefficients of thermal expansion, they also have the disadvantage of causing large warpage.

An object of the present invention is to provide a method for manufacturing a dielectric separation substrate that can produce a dielectric separation substrate without warping in a short time and with a small amount of growth gas.

[Means to solve the problem]

The present invention provides a method for manufacturing a dielectric isolation substrate using a single crystal silicon substrate having a crystal orientation (100), in which regions where elements including thyristors and transistors are to be formed are anisotropically etched and oxidized for the element isolation. a step of forming a film, a step of removing a portion of the oxide film to expose the single crystal silicon substrate, and growing silicon on the partially exposed surface of the single crystal silicon substrate by a vapor phase growth method. A step of forming a single crystal by annealing and further forming single crystal silicon by vapor phase growth in the element forming region and grinding a part of the deposited single crystal silicon.

The process includes a step of removing by polishing and forming an element isolation region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Figures (a) to (e) are sectional views of main parts shown in order of steps to explain the manufacturing method of the first embodiment of the present invention.

In the first embodiment, as shown in FIG. 1(a), first, a portion outside the element formation area is masked with an etching mask 1, and
The element forming region portion is anisotropically etched with an alkaline solution to form an etched element forming region 3.

The etching depth is several tens of μm.

Next, as shown in FIG. 1(b), the etching mask 1 is removed, an oxide film is formed on the anisotropically etched surface by thermal oxidation, and a part of the oxide film is etched (
100) Form the Si substrate exposed portion 5 to form portion #[4.

Next, as shown in FIG. 1(c), polycrystalline Si6 of several micrometers is deposited on the separation film 4 by vapor phase growth. It was formed by partially machining and nitching the separation M4 (
100) 5i (1, deposited single crystal Si7) near exposed portion 5 of Si substrate.

After that, the deposited polycrystalline Si is heated using a rapid heating lamp or the like.
Six sides are annealed to fully crystallize the deposited SL.

Next, as shown in FIG. 1(d), Si is grown to a thickness of several tens of μm on the processed Si substrate 2 by vapor phase growth.
A deposited single crystal 5i7a is formed.

Next, as shown in FIG. 1(e), A-
Grinding and polishing the single crystal 5i7a deposited up to the A' plane,
An element formation region 3a is formed.

According to such a method, it is not necessary to deposit Si for a long time, and since polycrystalline Si is not left on the substrate, there is very little warpage. Conventionally, the radius of curvature of warpage is several meters, but according to this embodiment, the radius of curvature can be suppressed to 10 meters or more.

FIGS. 2(a) to 2(e) are longitudinal cross-sectional views of main parts shown in order of steps to explain the manufacturing method of the second embodiment of the present invention.

In the second embodiment, as shown in FIG. 2(a), first, a portion where a power device or a vertical element is to be formed and a portion outside the element formation region to be separated are masked using an etching mask 1. The element formation region to be separated is anisotropically etched using an alkaline solution to form an etched element formation region 3.

Next, as shown in FIG. 2(b), the etching mask 1
is removed, a thermally oxidized film 4 is formed on the anisotropically etched surface, and a power device or vertical element formation portion of the separation film 4 is removed to form a (100) Si substrate exposed portion 5. .

Next, as shown in FIG. 2(C), Si is deposited to a thickness of several μm from above the separation [4] by vapor phase growth, and the deposited Si surface is annealed using a rapid heating lamp, etc. The entire surface of the deposited polycrystalline Si6 is made into a single crystal.

Next, as shown in FIG. 2(d), the processed (100
) Si is deposited on Si substrate 2 by vapor phase growth method (number + Jl m)
A deposited single crystal 5i7a is formed.

Next, as shown in FIG. 2(e), B-
Grinding and polishing the single crystal 5i7a deposited up to the B' plane,
An element formation region 8 that does not require separation from the element region 3a is formed.

According to such a method, a power element or a vertical element can be formed into two parts in separated element forming regions.

〔Effect of the invention〕

As explained above, the manufacturing method of the present invention includes (100)S
By anisotropically etching the element formation region on the i-substrate and depositing Si by vapor phase growth, it is possible to suppress warpage of the substrate and reduce manufacturing costs.

[Brief explanation of drawings]

1(a) to 1(e) are sectional views of main parts shown in the order of steps to explain the manufacturing method of the first embodiment of the present invention, and FIG. 2(a)
-(e) are cross-sectional views of main parts shown in order of steps to explain the manufacturing method of the second embodiment of the present invention, and FIGS. 3(a)-(d) are examples of the conventional manufacturing method of a dielectric isolation substrate. FIG. DESCRIPTION OF SYMBOLS 1... Etching mask, 2... (100) Sj substrate, 3... Etched element formation region, 3a...
・Element formation region, 4... Separation film, 5... (100)
Exposed portion of Si substrate, 6... Deposited polycrystalline Si, 7
゜7a... Deposited single crystal Si, 8... Element formation region that does not require separation, 9... Element formation region using (O) i substrate.

Claims (1)

[Claims] In a method for manufacturing a dielectric isolation substrate using a single crystal silicon substrate having a crystal orientation (100), an oxide film for element isolation is formed by anisotropically etching a region where elements including a thyristor or a transistor are to be formed. a step of removing a portion of the oxide film to expose the single crystal silicon substrate; and growing silicon on the partially exposed surface of the single crystal silicon substrate by a vapor phase growth method and forming the silicon by annealing. In the crystallization step and in the element formation region, further,
1. A method for manufacturing a dielectric isolation substrate, comprising the steps of forming single crystal silicon by vapor phase growth and removing a portion of the deposited single crystal silicon by grinding and polishing to form an element isolation region.