JPH03185841A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH03185841A
JPH03185841A JP32380289A JP32380289A JPH03185841A JP H03185841 A JPH03185841 A JP H03185841A JP 32380289 A JP32380289 A JP 32380289A JP 32380289 A JP32380289 A JP 32380289A JP H03185841 A JPH03185841 A JP H03185841A
Authority
JP
Japan
Prior art keywords
substrate
electrode
gate electrode
gas
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32380289A
Other languages
Japanese (ja)
Inventor
Koichi Sekida
関田 好一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP32380289A priority Critical patent/JPH03185841A/en
Publication of JPH03185841A publication Critical patent/JPH03185841A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To prevent deterioration of characteristics of an FET after a long time operation by a method wherein, after a gate electrode is formed, a dielectric film is formed, after the electrode surface is subjected to plasma discharge processing or heat treatment. CONSTITUTION:A positive type resist film 5 which is formed on the whole surface of a semiinsulative substrate composed of GaAs semiconductor single crystal and composed of organic polymer is fused and eliminated, and a metal layer 5 except an aperture part 5' is eliminated, thereby forming a gate electrode 7. The upper parts of the gate electrode 7, a source electrode 3 and a drain electrode 4, and the surface of the substrate 1 containing an exposed active layer 2 region between the source electrode 3 and the drain electrode 4 are subjected to plasma processing in oxygen gas or carbon tetrafluoride gas with a parallel plate type plasma equipment. The plasma processing in oxygen gas is performed under gas pressure of 0.48 torr and substrate temperature at 50 deg.C. The plasma processing in the carbon tetrafluoride is performed under gas pressure of 410 torr and substrate at a room temperature. A silicon nitride film 8 is formed on the whole surface of the active layer 2 by plasma CVD for 8 minutes using reaction between silane gas and nitrogen gas while the substrate 1 is heated at 230 deg.C.

Description

【発明の詳細な説明】[Detailed description of the invention]

[産業上の利用分野] 本発明は、ショットキー接合を形成するゲート電極を備
えた電界効果型トランジスタの製造方法に関し、特に、
保護用誘電体膜(パッシベーション膜)の形成方法に関
するものである。 〔従来の技術〕 GaAsなとの半導体上にショットキー接合を形成する
ゲート電極を備えた電界効果型トランジスタ(以下、F
ETという)は、高速動作に優れ、マイクロ波帯の増幅
素子として多く用いられている。このFETの表面には
、半導体表面および電極の保護のため、酸化シリコン、
窒化シリコンなどからなる保護用の誘電体膜を形成する
必要がある。 従来、これらのFETのゲート電極は、半導体表面にゲ
ート電極に対応する開口部を持ったマスク(レジスト膜
、または酸化シリコンなどの絶縁膜からなる)を形成し
、開口部およびマスク上に金属膜を形成し、次にマスク
を除去することでマスク上の金属膜を取り除き、開口部
にのみ金属膜を形成するリフトオフ法により形成される
。そして、保護用の誘電体膜の形成方法は、リフトオフ
法によりゲート電極を形成した後、半導体表面を有機溶
媒などにより洗浄し、スパッタリング法などにより保護
用の誘電体膜を形成するものである。 〔発明が解決しようとする課題] しかし、上記従来の方法で作成した保護用の誘電体膜を
用いたFETを長時間動作させると、高周波動作および
直流動作におけるFETの種々の特性が劣化することが
知られていた。 本発明は、上記の欠点を解決したもので、本発明の目的
は長時間動作後もFETの特性が劣化しない保護用誘電
体膜の形成方法を提供することにある。 [課題を解決するための手段および作用〕本発明は、保
護用の誘電体膜形成前にゲート電極および半導体前面に
何らかの処理をすることで、FETの特性劣化を防止で
きるとの着想に基づいたものである。 本発明は、半導体上にソース電極、ドレイン電極および
ショットキー接合を形成するゲート電極を備えた電界効
果型トランジスタの製造方法において、該ゲート電極を
リフトオフ法により形成する第1の工程、ソース電極と
ドレイン電極間の上記半導体の表面をプラズマ放電処理
または加熱処理する第2の工程、該表面上に誘電体膜を
形成する第3の工程を順次行なうものである。 第2の工程において、プラズマ放電処理は酸素、酸化雰
囲気を形成する化合物ガスまたはふっ素を含む炭素化合
物ガスの雰囲気中で行なわれる。また、加熱処理は、酸
化雰囲気で150℃から400℃程度に加熱することで
行なわれる。 本発明による作用は明らかではないが、FETの半導体
表面およびゲート電極表面が安定な酸化物またはふっ化
物に変化するため、その後に誘電体膜を形成すれば安定
な動作が可能になるものと考えられる。 〔実施例1 本発明の一実施例であるFETの製造工程を、第1図(
a)〜(c)を用いて以下に説明する。 半絶縁性のGaAs半導体単結晶からなる基板l上に0
.3μm程度の膜厚を有する導電性のGaAsエピタキ
シャル層からなる活性層2が形成されている。この活性
層2にオーミック接合するソース電極3およびドレイン
電極4が形成される。次に、基板1の全面に有機高分子
からなるポジ型のレジスト膜5を形成する。通常のフォ
トリソグラフィにより幅1μmの開口部5′が、このレ
ジスト膜5のソース電極3・ドレイン電極4間に形成さ
れる。そして、レジスト膜5上および活性層2がn出し
た開口部5′上に金属層6を形成する。(第1図(a)
) レジストM5を溶解除去し、開口部5′以外の金属層6
を取り去ることにより、開口部5′の領域に相当するゲ
ート電極7が形成される。(リフトオフ法) 次に、ゲート電極7、ソース電極3およびドレイン電極
4上、かつ、ソース電極3・ドレイン電極4間の露出し
た活性層2領域を含む基板lの表面を、平行板型プラズ
マ装置でプラズマ処理を行なう。プラズマ処理は、酸素
ガス中または四ふっ化炭素ガス中で行なう。(第1図(
b))この酸素ガス中のプラズマ処理は、ガス圧0゜4
8torr、基板温度50℃で5分間行なう。 また、四ふっ化炭素(CF、)ガス中のプラズマ処理は
、ガス圧410torr、基板温度は室温で1ないし5
分間行なう。なお、プラズマ処理の雰囲気は、酸素ガス
などの酸化雰囲気、または、CHF、など゛の含ふっ素
炭素化合物ガスを用いることができる。 その後、活性層2上の全面に厚さ1100nの窒化シリ
コン膜8(SiN)をプラズマCVDにより形成する。 このプラズマCVDは、基板lを230℃に加熱し、シ
ラン(S i H4)ガスと窒素ガスとの反応により約
8分間行なわれる。なお、保護用誘電体膜としては、窒
化シリコン膜以外に、酸化シリコン膜などの緻密な絶縁
膜を用いることができる。 ソース電極3およびドレイン電極4上の窒化シリコン膜
8を部分的に除去し、配線用金属9.9′を形成する。 (第1図(C)) 以上の実施例1の工程で作成したFETのゲート・ドレ
イン電極間のブレークダウン電圧の経時変化(ゲート・
ドレイン電極間に一定の逆方向電流(50mA)を流し
続けた場合)を実施例1として第2図に示す。また、プ
ラズマ処理を行なわず他の工程は上記実施例1と同一の
場合を比較例として記載した。 第2図かられかるように、比較例では、FETの作成直
後に一16Vであったブレークダウン電圧が、1800
分経過後には一10Vに悪化している。しかし、実施例
1はこのような劣化はみられず、ブレークダウン電圧は
約−16Vで一定であり、経時変化が生じていないこと
がわかる。 なお、上記の実施例1ではりフトオフによるゲート電極
の形成後にプラズマ処理を行っているが、他の実施例(
実施例2)としてこのプラズマ処理の替わりに酸素雰囲
気での加熱処理を行うことも可能である。 この酸素雰囲気での加熱処理は、大気雰囲気で基板1を
ヒータ(ホットプレートなど)により300℃程度の温
度に約1時間保持することで行われる。なお、この時の
雰囲気は、大気に限らず酸素を含む酸化性の雰囲気であ
れば良い。 この実施例2により作成したFETに一定の逆方向電流
を流し続けた場合のブレークダウン電圧の経時変化を第
3図に示す。また、比較例として、酸素雰囲気での加熱
処理を行なわず他の工程は上記実施例2と同一の場合を
比較例として記載した。 比較例では、第2図と同様の劣化がみられが、実施例2
のブレークダウン電圧は約−16Vで一定であり、実施
例1と同じく経時変化を生じないことがわかる。 なお、以上の実施例ではレジスト膜によるリフトオフ法
を用いているが、レジスト膜の替わりに酸化シリコン膜
などの絶縁膜を用いることも可能である。
[Industrial Application Field] The present invention relates to a method for manufacturing a field effect transistor having a gate electrode forming a Schottky junction, and in particular,
The present invention relates to a method of forming a protective dielectric film (passivation film). [Prior art] A field effect transistor (hereinafter referred to as F) is equipped with a gate electrode that forms a Schottky junction on a semiconductor such as GaAs.
(ET) has excellent high-speed operation and is often used as an amplification element in the microwave band. The surface of this FET is coated with silicon oxide to protect the semiconductor surface and electrodes.
It is necessary to form a protective dielectric film made of silicon nitride or the like. Conventionally, the gate electrodes of these FETs are formed by forming a mask (made of a resist film or an insulating film such as silicon oxide) on the semiconductor surface with an opening corresponding to the gate electrode, and then depositing a metal film over the opening and the mask. It is formed by a lift-off method in which the metal film on the mask is removed by forming and then removing the mask, and the metal film is formed only in the opening. The method for forming a protective dielectric film is to form a gate electrode by a lift-off method, then wash the semiconductor surface with an organic solvent or the like, and form a protective dielectric film by a sputtering method or the like. [Problems to be Solved by the Invention] However, when an FET using a protective dielectric film made by the above conventional method is operated for a long time, various characteristics of the FET in high frequency operation and DC operation deteriorate. was known. The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide a method for forming a protective dielectric film in which the characteristics of an FET do not deteriorate even after long-term operation. [Means and effects for solving the problem] The present invention is based on the idea that deterioration of FET characteristics can be prevented by performing some treatment on the gate electrode and the front surface of the semiconductor before forming a protective dielectric film. It is something. The present invention provides a method for manufacturing a field effect transistor having a source electrode, a drain electrode, and a gate electrode forming a Schottky junction on a semiconductor, including a first step of forming the gate electrode by a lift-off method; A second step of plasma discharge treatment or heat treatment of the surface of the semiconductor between the drain electrodes, and a third step of forming a dielectric film on the surface are sequentially performed. In the second step, the plasma discharge treatment is performed in an atmosphere of oxygen, a compound gas forming an oxidizing atmosphere, or a carbon compound gas containing fluorine. Further, the heat treatment is performed by heating from about 150° C. to 400° C. in an oxidizing atmosphere. Although the effect of the present invention is not clear, it is thought that since the semiconductor surface and gate electrode surface of the FET change into a stable oxide or fluoride, stable operation will be possible if a dielectric film is subsequently formed. It will be done. [Example 1] Fig. 1 (
This will be explained below using a) to (c). 0 on a substrate l made of semi-insulating GaAs semiconductor single crystal.
.. An active layer 2 is formed of a conductive GaAs epitaxial layer having a thickness of about 3 μm. A source electrode 3 and a drain electrode 4 are formed in ohmic contact with this active layer 2. Next, a positive resist film 5 made of an organic polymer is formed on the entire surface of the substrate 1. An opening 5' having a width of 1 μm is formed between the source electrode 3 and the drain electrode 4 of this resist film 5 by ordinary photolithography. Then, a metal layer 6 is formed on the resist film 5 and on the opening 5' of the active layer 2. (Figure 1(a)
) The resist M5 is dissolved and removed, and the metal layer 6 other than the opening 5' is removed.
By removing the gate electrode 7, a gate electrode 7 corresponding to the area of the opening 5' is formed. (Lift-off method) Next, the surface of the substrate l including the exposed active layer 2 region on the gate electrode 7, source electrode 3, and drain electrode 4 and between the source electrode 3 and drain electrode 4 is heated using a parallel plate plasma device. Perform plasma treatment. The plasma treatment is performed in oxygen gas or carbon tetrafluoride gas. (Figure 1 (
b)) This plasma treatment in oxygen gas is carried out at a gas pressure of 0°4.
This is carried out for 5 minutes at 8 torr and a substrate temperature of 50°C. In addition, plasma processing in carbon tetrafluoride (CF) gas is performed at a gas pressure of 410 torr and a substrate temperature of 1 to 5 torr at room temperature.
Do this for minutes. Note that an oxidizing atmosphere such as oxygen gas or a fluorine-containing carbon compound gas such as CHF can be used as the atmosphere for the plasma treatment. Thereafter, a silicon nitride film 8 (SiN) having a thickness of 1100 nm is formed on the entire surface of the active layer 2 by plasma CVD. This plasma CVD is performed for about 8 minutes by heating the substrate 1 to 230° C. and reacting silane (S i H 4 ) gas with nitrogen gas. Note that as the protective dielectric film, in addition to the silicon nitride film, a dense insulating film such as a silicon oxide film can be used. Silicon nitride film 8 on source electrode 3 and drain electrode 4 is partially removed to form wiring metal 9.9'. (Figure 1 (C)) Time-dependent change in breakdown voltage between the gate and drain electrodes of the FET fabricated through the process of Example 1 above (gate and drain electrodes)
FIG. 2 shows Example 1 in which a constant reverse current (50 mA) was continued to flow between the drain electrodes. Further, a case where the plasma treatment was not performed and the other steps were the same as in Example 1 was described as a comparative example. As can be seen from Figure 2, in the comparative example, the breakdown voltage, which was -16V immediately after fabrication of the FET, was 1800V.
After minutes, the voltage has deteriorated to -10V. However, in Example 1, such deterioration was not observed, and the breakdown voltage was constant at about -16V, indicating that no change occurred over time. Note that in Example 1 above, plasma treatment was performed after forming the gate electrode by beam lift-off, but other examples (
As Example 2), it is also possible to perform heat treatment in an oxygen atmosphere instead of this plasma treatment. This heat treatment in an oxygen atmosphere is performed by maintaining the substrate 1 at a temperature of about 300° C. for about 1 hour using a heater (such as a hot plate) in an air atmosphere. Note that the atmosphere at this time is not limited to the air, but may be any oxidizing atmosphere containing oxygen. FIG. 3 shows the change in breakdown voltage over time when a constant reverse current continues to flow through the FET manufactured according to Example 2. Further, as a comparative example, a case in which heat treatment in an oxygen atmosphere was not performed and other steps were the same as in Example 2 was described as a comparative example. In the comparative example, the same deterioration as shown in Fig. 2 was observed, but in the example 2
It can be seen that the breakdown voltage is constant at about -16V and does not change over time as in Example 1. Note that although the above embodiment uses a lift-off method using a resist film, it is also possible to use an insulating film such as a silicon oxide film instead of the resist film.

【発明の効果】【Effect of the invention】

゛1以上説明したように、本発明は、半導体上にソース
電極、ドレイン電極およびショットキー接合を形成する
ゲート電極を備えた電界効果型トランジスタの製造方法
において、該ゲート電極をリフトオフにより形成する第
1の工程、ソース電極とドレイン電極間の上記半導体の
表面をプラズマ放電処理または加熱処理する第2の工程
、該表面上に誘電体膜を形成する第3の工程を順次行な
うものである。 したがって、本発明による電界効果型トランジスタは長
時間の動作後もその特性は劣化せず、安定した動作特性
が得られるものである。
1. As explained above, the present invention provides a method for manufacturing a field effect transistor having a source electrode, a drain electrode, and a gate electrode forming a Schottky junction on a semiconductor. The first step, the second step of plasma discharge treatment or heat treatment of the surface of the semiconductor between the source electrode and the drain electrode, and the third step of forming a dielectric film on the surface are sequentially performed. Therefore, the characteristics of the field effect transistor according to the present invention do not deteriorate even after long-time operation, and stable operating characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(C)は、本発明の一実施例を説明する
ための断面図、 第2図および第3図は、実施例と比較例のブレークダウ
ン電圧の経時変化を示す図である。 図において、 l・・・基板、2・・・活性層、3・・・ソース電極、
4・・・ドレイン電極、5・・・レジスト膜、5′・・
・開口部、6・・・金属層、7・・・ゲート電極、8・
・・窒化シリコン膜、9.9′・・・配線用金属。
FIGS. 1(a) to (C) are cross-sectional views for explaining one embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing changes over time in the breakdown voltage of the embodiment and the comparative example. It is. In the figure, l...substrate, 2... active layer, 3... source electrode,
4...Drain electrode, 5...Resist film, 5'...
・Opening portion, 6... Metal layer, 7... Gate electrode, 8.
...Silicon nitride film, 9.9'...Metal for wiring.

Claims (1)

【特許請求の範囲】[Claims]  半導体上にソース電極、ドレイン電極およびショット
キー接合を形成するゲート電極を備えた電界効果型トラ
ンジスタの製造方法において、該ゲート電極をリフトオ
フ法により形成する第1の工程、ソース電極とドレイン
電極間の上記半導体の表面をプラズマ放電処理または加
熱処理する第2の工程、該表面上に誘電体膜を形成する
第3の工程を順次行なうことを特徴とした半導体装置の
製造方法。
In a method for manufacturing a field effect transistor having a source electrode, a drain electrode, and a gate electrode forming a Schottky junction on a semiconductor, a first step of forming the gate electrode by a lift-off method, a step of forming the gate electrode between the source electrode and the drain electrode; A method for manufacturing a semiconductor device, comprising sequentially performing a second step of plasma discharge treatment or heat treatment on the surface of the semiconductor, and a third step of forming a dielectric film on the surface.
JP32380289A 1989-12-15 1989-12-15 Manufacture of semiconductor device Pending JPH03185841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32380289A JPH03185841A (en) 1989-12-15 1989-12-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32380289A JPH03185841A (en) 1989-12-15 1989-12-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03185841A true JPH03185841A (en) 1991-08-13

Family

ID=18158774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32380289A Pending JPH03185841A (en) 1989-12-15 1989-12-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03185841A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235559B1 (en) * 1997-08-05 2001-05-22 International Business Machines Corp. Thin film transistor with carbonaceous gate dielectric

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235559B1 (en) * 1997-08-05 2001-05-22 International Business Machines Corp. Thin film transistor with carbonaceous gate dielectric

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