JPH03185873A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To miniaturize a semiconductor device while reducing the metallic wirings by a method wherein a groove is cut in the surface of a substrate; a MOS type transistor having a channel is formed in vertical direction on both sides of the groove; and a drain and a source are commonly used. CONSTITUTION:Field oxide films 2 for isolating elements is formed on the specific positions of a P type silicon substrate 1. Later, a groove 4 is formed by dry-etching the silicon substrate 1 using a photoresist pattern as a mask. Next, an enhancement type transistor is formed by implanting boron ions meeting the requirements for impressed energy of 30keV, the dosage of 3X10<12>cm<-2> to control the threshold value voltage. At this time, it is recommended that the sides of the groove 4 are made vertical as much as possible for the ion implantation preferably performing two time spinning implantation process to assure the even implantation on both sides. Later, a drain source diffused layer 10, a source diffused layer 6 and a drain diffused layer 8 are formed by leading-in phosphorus or arsenic by ion-implantation process or thermal diffusion process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, a novel MOS transistor structure capable of achieving higher integration and a method for manufacturing the same. Conventional technology Figure 5 is a cross-sectional view showing the structure of a CMOS type inverter, which is one of the conventional examples. 2 is an insulating region for separating each element. 3 is a P-type silicon substrate. 11 is a gate insulator 12 is a gate electrode plate 16 made of a polycrystalline silicon film is an interlayer insulator JEiL 17~
20 is each gate, source, and drain electrode;
18 is a metal wiring connecting two MOS transistors. In a conventional CMOS type O3 converter configured as above? ;t,, The channel, source, and drain of the MO5 type transistor are formed linearly on the surface of the silicon substrate 1, and furthermore, in order to insulate and isolate each MOS type transistor, an element isolation region 2 is formed using LOGO3 technology or trench technology. Even if an MO5 type transistor is provided, the MO5 type transistor is covered with an interlayer insulating film 16. Each element is connected by making contact between the metal wiring on this interlayer insulating film 16 and the MO8 type transistor.

Problems to be Solved by the Invention However, when attempting to integrate a J&MO5 type semiconductor device with the above configuration, it is necessary to reduce the channel length element isolation region. Narrowing the element isolation region causes problems such as dielectric breakdown.Furthermore,:
= There are steps on the substrate surface and interlayer insulating film for MOSMOS transistors and element isolation regions, and metal wiring must be formed on these steps.This may cause disconnections or shorts in the wiring. SUMMARY OF THE INVENTION The present invention has been made in consideration of these points, and an object of the present invention is to provide a semiconductor device having a novel structure in which the size of the semiconductor device is miniaturized and metal wiring is reduced without reducing the gate size or element isolation region, and a method for manufacturing the same. Means for Solving the Problems The present invention is a friend of the present invention A means for achieving the above object A groove is dug in the surface of a substrate, and MOS transistors having channels perpendicular to the surface are formed on both sides of the groove. Drain,
The present invention has the above-described structure, and the channel of the MO8 type transistor is set perpendicular to the substrate surface, and the source, By sharing the drain, the area is reduced, and by directly connecting the gate electrode and the source and drain, the metal wiring is reduced.Example (Example 1) Figure 1 shows an N-channel diagram in the first example of the present invention. E of
Figure 1(a) is a process cross-sectional view showing a manufacturing method for an E-type inverter. After forming the field oxide film 2, the silicon substrate 1 is etched by dry etching using the photoresist pattern as a mask to form the grooves 4. Both sides of groove 4 ((0
10) Threshold voltage control on plane> Implant energy: 30 KeV.

Boron ions were implanted at a dose of 3 x 10"cm-" to form an enhancement type transistor.At this time, the sides of trench 4 were oxidized before implantation, and this oxide film was removed after implantation. (1) It is desirable that the ion implantation be perpendicular to the side surfaces of the groove 4 as much as possible, and the implantation is performed twice so that both sides are evenly implanted. After this, phosphorus or Arsenic is introduced to form the drain/source diffusion layer 1O, the source diffusion layer 6, and the drain diffusion layer 8, but dry oxidation or After forming the oxide film 11 using wet oxidation, the oxide film on one of the drain diffusion layers 8 is removed by etching using a photoresist pattern as a mask.

In FIG. 1(d), a portion of the trench 4 is then filled by depositing a polycrystalline silicon film by the well-known vapor phase growth method and using an etch-back method. Polycrystalline silicon other than the upper part of the film is removed by dry etching. Next, using the photoresist pattern as a mask, the polycrystalline silicon is etched by dry etching (RIE) until it reaches the source/drain diffusion layer 1O, the polycrystalline silicon on both sides is separated, and the two gate electrodes 1 are etched.
2, but it is also possible to use ion beam etching with good directivity and excellent microfabrication.
), the surface of the gate electrode 12 and the bottom surface of the trench 4 are oxidized using dry oxidation or wet oxidation to form an oxide film 1 on the bottom surface.
Etch 1 using the photoresist pattern as a mask
Next, the contact openings created by this step are filled with aluminum 14 using sputtering.Although it is also possible to use other metals at this time, an oxide film 16 is then deposited on the surface of the device using a vapor phase growth method. At least, an electrode 17 is formed by forming a contact hole at a desired position by photolithography.
In the E/E type MOS inverter of this embodiment configured as described above, the source and drain of two MO8 type transistors are shared by the drain/source diffusion layer 10. Although it is possible to reduce the amount of metal wiring by directly connecting one gate electrode and the drain 8 (Embodiment 2), FIG.
Figure 2 (a) is a cross-sectional view of the manufacturing process for a D-type inverter! A field oxide film 2 for isolation between elements is formed at a desired position on a P-type silicon substrate l having a (100) plane by a well-known selective oxidation method, and then the silicon substrate is removed by dry etching using a photoresist pattern as a mask. Etching to form groove 4
As shown in Figure 2(b), photoresist pattern 5 is used so that the four groove planes are (010) and (001) planes.1. % Threshold voltage control plate on one side of groove 4 ((010) plane) Implant energy: 30 KeV,
Boron ions are implanted at a dose of 3 x 10"cm to form an enhancement type transistor, but at this time, the side surfaces of trench 4 are oxidized before implantation, and this oxide film is removed after implantation. Good (1) It is desirable that the ion implantation be perpendicular to the side surface of the groove 4 as much as possible.
Phosphorus or arsenic is introduced by ion implantation or thermal diffusion to form the drain/source diffusion layer 9 and the source diffusion layer 6. The other side is similarly implanted with an implantation energy of 30 K.
Threshold voltage control (depression type) by boron ion implantation and formation of the drain/source diffusion layer 10 and the drain diffusion layer 8 are carried out under the conditions of a dose of 1×lO"cm-'.

In FIG. 2(C), the surface of the semiconductor substrate 1 and the side surfaces of the groove 4 are oxidized using dry oxidation or wet oxidation. Next, half of the oxide film 11 on the bottom of the groove 4 is covered with a photoresist pattern. In this case, dry etching with excellent directivity or ion beam etching can be used as a mask. After that, using the photoresist pattern as a mask, polycrystalline silicon other than the top of trench 4 is removed by dry etching.Next, using the photoresist pattern as a mask, dry etching is performed to remove the source/drain diffusion layer 9.10. The polycrystalline silicon is etched until the polycrystalline silicon is etched on both sides, and the two gate electrodes 12 are formed. In FIG. 2(e), the contact hole 13 created in the previous step is filled with an oxide film 15 using the well-known vapor phase growth method.
Further, the surface of the semiconductor device is covered with an oxide film 16. Next, open contact holes at desired positions. Electrodes 17, 18, 1.9,
In the E/D type MOS inverter of this embodiment configured as above, the source and drain of the two MO8 type transistors are shared by the drain/source diffusion layer 9 and 10, and the depletion type transistor is formed. By connecting the gate electrode I8 of the transistor directly to the source 10 on the bottom surface of the trench 4, it is possible to reduce the number of metal wirings (Embodiment 3).
FIG. 3 is a process cross-sectional view showing a method for manufacturing a barter.

In Fig. 3(a), phosphorus ions are implanted into a silicon substrate l having a C-P type (100) plane using a photoresist pattern as a mask, and heat treatment is performed to diffuse the phosphorus ions and form an N-well diffusion region 3. do. Thereafter, a field oxide film 2 for isolation between elements is formed at a desired position on the silicon substrate 1 using a well-known selective oxidation method, and then a groove 4 is formed by etching the silicon substrate by dry etching using the photoresist pattern as a mask. At this time, the four grooves are arranged so that the planes are (010) and (001'). Threshold voltage control on (010) plane Implant energy: 30 Key, dose: 3 x 10”cm
In this case, it is possible to oxidize the side surfaces of the groove 4 before implantation and remove this oxide film after implantation (1) The ion implantation should be performed perpendicularly to the side surfaces of the groove as much as possible. Next, arsenic ions are implanted into the surface of the semi-dead substrate 1, the bottom of the trench 4, and the substrate surface to form the source diffusion region 6 and drain diffusion region 9.The same applies to the P-type side surface of the trench 4. The source diffusion region 26 and the drain diffusion region 10 are formed by implanting boron ions, and in FIG. Oxidize M using dry oxidation or wet oxidation to
11 is formed. Next, a part of the groove 4 is filled by depositing polycrystalline silicon by a well-known vapor phase growth method and using an etch-back method. After this, using the photoresist pattern as a mask, the upper part of the groove 4 or Polycrystalline silicon other than the upper part of the contact groove is removed by dry etching.

In FIG. 3(d), using the photoresist pattern as a mask, the polycrystalline silicon is etched by dry etching until it reaches the drain diffusion layer 9 and 10, forming a common gate electrode 12. At this time, the directivity is fine and fine processing is performed. It is also possible to use ion beam etching, which is excellent for 1.%
Thereafter, the surface of the polycrystalline silicon and the bottom of the contact hole are oxidized using dry oxidation or wet oxidation, and the oxide film 11 on the bottom is etched using the photoresist pattern as a mask.

In FIG. 3(e), the contact hole 13 created in step 4(D) is filled with aluminum 14 using a sputtering method. At this time, it is also possible to use other metals. This process is completed by depositing an oxide film 16 using a growth method and forming contact holes at desired positions using a photolithography method. In the example CMOS type inverter, two MO5
By sharing the drains of type transistors, metal wiring can be reduced (Embodiment 4) FIG. 4 is a process cross-sectional view showing a method of manufacturing a CMOS type inverter according to a fourth embodiment of the present invention. Figure 3 (a
)~(C) Process characteristics In Figure 4(a), the polycrystalline silicon is etched using the photoresist pattern as a mask until it penetrates through the source diffusion layer 9 and 10 by dry etching. layer 9
．． Separate the IO and form the two gate electrodes 12.
At this time, an ion beam with good directivity and excellent microfabrication
Etching may also be used.1 After this, the surface of the polycrystalline silicon is oxidized using dry oxidation or wet oxidation, and the oxide film 11 on the bottom surface is etched using the photoresist pattern as a mask. The contact opening 13 created in the process shown in FIG. In the CMOS type inverter of this embodiment configured as above, the contact hole 1 is formed at a desired position by the etching method, the electrodes 17, 18, 20 are connected, and the groove 4 is completed. By setting the source region 9 of the N-channel MOS transistor and the source region 10 of the P-channel transistor provided on the bottom surface of the substrate to the same potential as the respective substrates, the voltage is set to OV in the silicon substrate 1 and 5V in the N well 3. There is no need to form an electrode in this part1.Also, the distance between the source region 10 of the P-channel MOS transistor and the P-type substrate l is shortened.
Even though the latch-up characteristics are excellent, the present invention has more advantages than the present invention.By forming a groove on the substrate surface and forming MOS transistors with vertical channels on both sides of the groove, the surface area can be reduced. Also, the drain of one MO5 type transistor and the source of the other MO8 type transistor are shared, and further MO8
By directly connecting the gate electrode and drain of a type transistor, it is possible to reduce the amount of metal wiring, and the practical effect is 1.

[Brief explanation of drawings]

Figure 1 shows the manufacturing process of an E/E type inverter, which is the first embodiment of the present invention. Figure 2 shows the manufacturing process of the E/D type inverter, which is the second embodiment of the invention. Third aspect of the present invention
Figure 4 shows the manufacturing process of a CMOS type inverter, which is an embodiment of the present invention. Figure 5 shows the manufacturing process of a CMOS type inverter, which is a fourth example of the present invention.
A cross-sectional view of the structure of a type inverter

Claims (8)

[Claims] (1) Source and drain diffusion regions formed on the top and bottom surfaces of a trench formed in a semiconductor substrate, and gate insulating films formed on both sides of the trench, and a MOS type A semiconductor device made up of transistors. (2) The semiconductor device according to claim 1, wherein enhancement type MOS transistors are formed on both sides of the trench. (3) The semiconductor device according to claim 1, wherein an enhancement type MOS transistor is formed on one side of the trench, and a depletion type MOS transistor is formed on the other side. (4) The semiconductor device according to claim 1, wherein an N-type MOS transistor is formed on one side of the trench, and a P-type MOS transistor is formed on the other side. (5) forming a groove in the semiconductor substrate; forming a source and a drain on the top and bottom surfaces of the groove; and covering the substrate surface, the bottom and side surfaces of the groove with an oxide film; The gates on both sides are removed by removing the oxide film on the formed drain, and then filling a part of the trench with gate metal and etching the gate metal in the center of the trench down to the source and drain at the bottom of the trench. a step of separating the metal; a step of covering the surface of the gate metal with an oxide film and removing the oxide film at the bottom of the formed contact hole by etching; and after filling the etched hole with the metal, the surface of the semiconductor device is removed. A method of manufacturing a semiconductor device, comprising the steps of: covering the semiconductor device with an oxide film and forming a contact hole at a desired position to form an E/E type inverter. (6) forming a groove in a semiconductor substrate; forming a source and a drain on the upper surface and bottom surface of the groove; and covering the substrate surface, the bottom surface and side surfaces of the groove with an oxide film, After that, the trench is filled with gate metal, and the gate metal on both sides is separated by etching the gate metal in the center of the trench down to the source and drain at the bottom of the trench. and a step of filling the contact hole formed by etching with an oxide film, covering the surface of the semiconductor device with an oxide film, and forming the contact hole at a desired position to form an E/D type inverter. A method for manufacturing a semiconductor device, characterized in that: (7) Forming a diffusion region of another conductivity type in a semiconductor substrate of one conductivity type, forming a groove at the boundary between the diffusion region of another conductivity type and the semiconductor substrate of one conductivity type, and forming a source on the upper surface of the groove and a source on the bottom surface of the groove. a step of forming a drain, and a step of covering the substrate surface, the bottom and side surfaces of the trench with an oxide film, filling it with gate metal, and etching the gate metal in the center of the trench down to the source and drain at the bottom of the trench. , a step of covering the surface of the gate metal with an oxide film and removing the oxide film at the bottom of the contact hole formed by etching, and covering the surface of the semiconductor device with an oxide film after filling the etching hole with metal; 1. A method of manufacturing a semiconductor device, comprising the step of forming a contact hole at a desired position, and forming a CMOS type inverter. (8) A step of forming a diffusion region of another conductivity type in a semiconductor substrate of one conductivity type, a step of forming a groove at the boundary between the diffusion region of another conductivity type and the semiconductor substrate of one conductivity type, and a step of forming a drain on the upper surface of the groove. forming a source on the bottom surface;
The bottom and side surfaces of the trench are covered with an oxide film and then filled with gate metal, and the gate metal in the center of the trench is etched down to the bottom of the source and drain of the trench, thereby removing the gate metal on both sides and the bottom of the hole. After that, the contact hole formed by etching is filled with an oxide film, and the surface of the semiconductor device is covered with the oxide film.
C. forming a contact hole at a desired position;
A method of manufacturing a semiconductor device, comprising forming a MOS type inverter.