JPH03185919A - First stage input circuit - Google Patents

Abstract

PURPOSE:To obtain a stable characteristic as specifications by providing plural fuse elements and blowing out a fuse element when a level of an input signal is improper so as to vary the capability of a 1st stage input transistor(TR). CONSTITUTION:A P-channel MOS TR1, an N-channel MOS TR2, and a P- channel MOS TR1<1>, an N-channel MOS TR2<1> are connected respectively in series and fuse elements 5, 6 are connected in series between the TRs 1<1>,1<2>. Then an input signal phiIN is measured with respect to a VIH and VIL and when the input signal has no margin with respect to the VIH or the input signal reaches the specification of 2.4V or over, the element 5 is blown out by using a laser, the level of the input signal is shifted advantageous with respect to the VIH specification. Moreover, when the input signal has no margin with respect to the VIL or the input signal reaches the specification of 0.8V or less, the element 6 is blown out by using a laser, the level of the input signal is shifted advantageous with respect to the VIL specification, thereby obtaining a proper input characteristic of the 1st stage input circuit.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a first stage input circuit.

[Conventional technology]

A conventional first-stage input circuit of this type, as shown in FIG. When the input signal φ■N is at a LOW level, the output signal φ1 is at a high level, and conversely, when the input signal φIN is at a high level, the output signal φl is at a high level. L.O.
It becomes W level.

Here, the gates of transistors 1 and 2 are commonly connected,
It is connected to the input terminal 3, and the connection point of the series body of transistors 1 and 2 is connected to the output terminal 4.

[Problem to be solved by the invention]

In the conventional first-stage input circuit described above, the input signal φIN
is at least 2.4V as VIH.

VIL requires at most 0.8V.

Now, if the manufacturing conditions shift in such a way that the ability of P-channel MO3 transistor 1 becomes smaller and the ability of N-channel MO3 transistor 2 becomes larger, input signal φI
There was no margin for N's VIL spec of 0.8V, or the level was lower than that. Furthermore, there was an accident in which the output did not reach a high level with an input of 0.8V. If the manufacturing conditions shift in such a way that the capacity of P-channel MO3 transistor 2 increases and the capacity of N-channel MO3 transistor 2 decreases, there may be no margin for input signal φIN with respect to the VIH specification of 2.4V, or It has drawbacks that go above and beyond. In other words, specifications
There was an accident where the output did not go to a low level with the 2.4V input.

SUMMARY OF THE INVENTION An object of the present invention is to provide a first-stage input circuit which solves the above-mentioned drawbacks and has stable characteristics according to the spacing.

[Means to solve the problem]

The configuration of the first stage input circuit of the present invention is as follows. A first series body consisting of a second MOS transistor, a third MOS transistor, a first . A second series body including a second phase element and a fourth MOS transistor, and a connection point between the first series body and the first series body. The connection points of the second phase elements are connected to each other to form an output, and the first to fourth
The gates of the MOS transistors are connected to each other and used as an input.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 is a circuit diagram showing a first stage input circuit according to a first embodiment of the present invention. In FIG. 1, the first stage input circuit of the first embodiment includes an input terminal 3 to which an input signal φIN is applied;
The circuit includes an output terminal 4 to which an output signal φ1 is output, a P-channel MO3 transistor 1.1', an N-channel MO3 transistor 2.2', and a phase element 5.6. Here, the transistor 1.2 and the transistors l' and 2' are each connected in series, and a phase element 5.6 is further connected in series between the transistors 1' and 2', and their common connection is The point is output terminal 4
It is connected to the. The gate of transistor 1゜1',
The gates of transistors 2 and 2' are connected to each other,
Connect to input terminal 3.

First, in a semiconductor wafer state, V I of input signal φIN
H, and VIL are measured, and for VIH,
If there is no margin, or if the voltage is higher than the spec value of 2.4 V, the phase element 5 can be cut using a laser and shifted advantageously with respect to the VIH spec.

In addition, if there is no margin for VIL or if it is below the spec value of 0.8V, the phase element 2
' can be cut using a laser and shifted advantageously with respect to the VIL specifications. Phase element 5.
When 6 is disconnected, transistors 1' and 2' each become inoperative.

The first-stage input circuit of this embodiment has means for changing the capability of the first-stage input transistor in a semiconductor wafer state, so that highly reliable operation can be ensured.

FIG. 2 is a circuit diagram showing a first stage input circuit according to a second embodiment of the present invention.

In FIG. 2, the first stage input circuit of this embodiment is of the NOR type, and includes a P channel MO3) transistor 1. 1', 7, an N-channel MO3 transistor 2.2', 8, and a phase element 5.6. The input signal φ2 is applied to the gate terminal 13 of the transistor 7, and the input signal φ2 is also applied to the gate terminal 11 of the transistor 8. transistor 7
The other pole is connected to one pole of transistor 1.1', and one pole of transistor 7 is connected to the Vcc power supply. Transistor 8 is connected in parallel with transistor 2.2'.

FIG. 3 is a circuit diagram showing a first stage input circuit according to a third embodiment of the present invention. In FIG. 3, the first stage input circuit of this embodiment is of the NAND type, and includes P-channel MO3 transistors 1.1' and 9, and N-channel MO3 transistors 2.1' and 9. 2' and 10.

Here, transistor 9 is connected in parallel with transistor 1, and its gate is connected to input terminal 14 to which input signal φ3 is applied, and transistor 10 is connected in series with transistor 2, and its gate is connected to input terminal 14, to which input signal φ3 is applied. It is connected to input terminal 6-l2 to which signal φ3 is applied.

In the second and third embodiments, similarly to the first embodiment,
For normal operation, the phase element 5.6 can be fused and used as appropriate. That is, VIH or VIL of the human signal
can be changed.

〔Effect of the invention〕

As explained above, in the present invention, a plurality of phase elements are prepared, and VIH of an input signal is adjusted in a semiconductor wafer state.
, VIL are inappropriate, cutting off the phase element and changing the capability of the first-stage input transistor has the effect of obtaining appropriate input characteristics of the first-stage input circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first-stage input circuit of a first embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing first-stage input circuits of second and third embodiments of the present invention, respectively. FIG. 4 is a circuit diagram showing a conventional first-stage input circuit. 3.11, 12.13.14... Input terminal, 4
...Output terminal, φIN...Input signal,
φ1...First stage output signal, Vcc...Power supply voltage, 1. 1', 7゜9...P channel MO3 transistor, 2゜2', 10...
N-channel MO3 transistor, 5.6...
Phase element, φ2. φ3...Control input signal.

Claims (1)

[Claims] a first series body consisting of first and second MOS transistors; a second series body consisting of a third MOS transistor, first and second phase elements, and a fourth MOS transistor; The connection points of the series bodies and the first and second
A first-stage input circuit characterized in that the connection points of the phase elements are connected to each other to form an output, and the gates of the first to fourth MOS transistors are connected to each other to form an input.