JPH03186022A - Fault detector - Google Patents

Abstract

PURPOSE:To detect faults of a transmission circuit and a reception circuit even when a sent signal and a received signal are sent/received by comparing a monitoring signal multiplexed with the sent signal with a monitoring signal demultiplexed from the received signal and detecting the faults of the transmission circuit and reception circuits. CONSTITUTION:The monitoring signal is multiplexed with the sent signal whose speed is converted into high-speed and inputted to the transmission circuit 6 which performs fault detection and the monitoring signal is demultiplexed from the output signal of the transmission circuit 6 and sent back. The monitoring signal is multiplexed with the received signal whose speed is converted into the high-speed and inputted to the reception circuit 7 which performs the fault detection. Further, the monitoring signal is demultiplexed from the output signal of the reception circuit 7 and compared with the monitoring signal multiplexed with the received signal to detect the faults of the transmission circuit 6 and reception circuit 7. Thus, while the sent signal and received signal are sent and received normally, the fault of the transmission circuit and reception circuit can be detected at all times.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a failure detection device that detects a failure in a transmitting circuit and a receiving circuit that control an interface with a communication line when a communication device is connected to a communication line. It is something.

[Conventional technology]

FIG. 3 is a configuration diagram showing a conventional failure detection device disclosed in, for example, Japanese Patent Application Laid-Open No. 63-99638.

In the figure, 1 is a transmission signal input terminal to which a transmission signal from a communication device (not shown) is input, and 2Fi is a reception signal output terminal to which a reception signal to the communication device is output. 3 is a transmission signal output terminal to which a transmission signal to a communication line (not shown) is output, and 4 is a reception signal input terminal to which a reception signal from the communication line is input. Reference numeral 5 denotes a line interface for connecting these transmitted signals and received signals to a communication line.

Reference numeral 6 denotes a transmitting circuit that performs processing necessary for transmission such as encoding on the transmitting signal inputted through the transmitting signal input terminal 1, and sends it to the circuit interface 5; 7 denotes the circuit interface 5.
This is a receiving circuit that performs necessary processing such as decoding on the received signal from the receiver and sends it to the received signal output terminal 2. The fault detection device detects faults in the transmitting circuit 6 button and the receiving circuit 7.

On the other hand, 10 is a received signal detection circuit that detects whether or not a received signal is input to the received signal input terminal 4 and sends out a control signal. 11 is switched by a control signal from the received signal detection circuit 10, and selects either the received signal sent via the line interface 5 or the return signal directly returned from the transmission circuit 6. , is a selection circuit input to the receiving circuit 7. Reference numeral 12 denotes a delay circuit that branches the transmission signal input to the transmission signal input terminal 1 and gives it a delay time corresponding to the transit time between the transmission circuit 6 and the reception circuit 7.

13 responds to the control signal from the received signal detection circuit 10,
A comparison circuit 14 detects the presence or absence of a fault by comparing the return signal from the transmitting circuit 6 processed by the receiving circuit 1 and the output signal of the delay circuit 12, and outputs the fault detection result. This is a detection result output terminal to which a detection result is output. Reference numeral 15 denotes an output control circuit that outputs the received signal input to the received signal input terminal 4 and processed by the receiving circuit γ to the received signal output terminal 2 in accordance with a control signal from the received signal detection circuit 10.

Next, the operation will be explained. 1. Transmission signal input terminal 1
The transmission signal input from the communication device is subjected to processing necessary for transmission such as encoding in the transmission circuit 6, and is outputted to the transmission signal output terminal 3 and the communication line through the line interface 5. At this time, the signal outputted from the transmitting circuit 6 is further directly reflected and inputted to the selection circuit 11 as well. and,
The selection circuit 11 receives the input signal from the reception signal input terminal 4 that has passed through the line interface 5 and the transmission signal input terminal 1 that has passed through the transmission circuit 6, and receives the control signal output from the reception signal detection circuit 10. When the received signal input terminal 4 does not indicate that a received signal is present, the output of the transmitting circuit 6 is selected, and when the control signal indicates that a received signal is present, the line interface 5 is selected.
The received signal input terminal 4 that has passed through is selected and outputted to the receiving circuit T. The receiving circuit 7 subjects the signal output from the selection circuit 11 to processing necessary for reception, such as decoding, and outputs it to the comparison circuit 13 and output control circuit 15.

The comparison circuit 13 also includes a delay circuit that delays the transmission signal input to the transmission signal input terminal 1 by the sum of the processing time in the transmission circuit 6 and the processing time in the button and reception circuits 7. 12 output signals are also input. Comparison circuit 13
When the control signal output from the received signal detection circuit 10 does not indicate that a received signal is present at the received signal input terminal 4, a failure in the transmitting circuit 6 and the receiving circuit 7 is detected by comparing the two. and outputs the fault detection result to the detection result output terminal 14. On the other hand, in the output control circuit 15,
When the control signal output from the received signal detection circuit 10 indicates that a received signal is present at the received signal input terminal 4, the output of the receiving circuit T is outputted from the received signal output terminal 2 to the communication device. do.

[Problem to be solved by the invention]

Since the conventional fault detection device is configured as described above, it is impossible to detect faults in the transmitting circuit 6 and the receiving circuit T while transmitting and receiving signals, and the received signal is not input to the received signal input terminal 4. Since fault detection for the transmitting circuit 6 and receiving circuit T is performed only during non-existent time periods, if the received signal is constantly input to the received signal input terminal 4, no fault detection is performed at all. There was a problem.

This invention has been made to solve the above-mentioned problems, and provides a fault detection device that can constantly detect faults in the transmitting circuit and the receiving circuit while performing normal transmission and reception of transmitted and received signals. With the goal.

[Means to solve the problem]

A fault detection device according to the present invention includes a first speed conversion circuit and a first multiplex circuit that convert the speed of a transmission signal input to a transmission circuit to a higher speed and multiplex a monitoring signal, and a transmission circuit. A first separating circuit separates the signal output from the transmitter into a transmitting signal and a monitoring signal, and returns the transmitting signal to its original speed. A third speed conversion circuit that converts the speed to a higher speed and multiplexes the monitoring signal separated by the first separation circuit, and a second multiplexing circuit, and converts the signal output from the reception circuit into a reception signal. a second separation circuit which separates the received signal into a monitoring signal and returns the speed of the received signal to the original speed; and a fourth speed conversion circuit; and a check circuit that compares the separated monitoring signal with the monitoring signal and outputs a fault detection result.

[Effect]

The fault detection device of the present invention multiplexes and inputs a monitoring signal to a transmission signal which has been speed-converted to a high speed, into a transmission circuit where a fault is detected, and converts it into a transmission signal at the output end of the transmission circuit. and a monitoring signal, the transmission signal is returned to its original speed and output, and the monitoring signal is looped back to the reception circuit where fault detection is performed, and the speed conversion is performed and the reception signal is returned to a higher speed. The monitoring signal is multiplexed and inputted, and at the output end of the receiving circuit, it is separated into a received signal and a monitoring signal, and the received signal is returned to its original speed and output, and the monitoring signal multiplexed with the transmitted signal is By comparing the received signal and the separated monitoring signal to detect failures in the transmitting circuit and receiving circuit, it is possible to detect failures in the transmitting circuit and receiving circuit even when transmitting and receiving signals are being transmitted and received. Realizing a fault detection device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. vg
In the figure, 1 is a transmission signal input terminal, 2 is a reception signal output terminal, 3 is a transmission signal output terminal, 4 is a reception signal input terminal, 5 is a line interface, 6 is a transmission circuit, T is a reception circuit, and 14 is a detection circuit. Since the result output terminal is the same as or corresponds to the conventional one denoted by the same reference numeral in FIG. 3, a detailed explanation will be omitted.

20 is a transmission signal input terminal 1 from a communication device (not shown)
21 is a first speed conversion circuit that converts the speed of a transmission signal inputted into a higher speed one, and 21 multiplexes a monitoring signal with the transmission signal speed-converted by this first speed conversion circuit 20; This is the first multiplex circuit that supplies the transmitting circuit 6 where fault detection is performed.

22 is a supervisory signal generation circuit that generates the supervisory signal υ
An example of this monitoring signal is a pseudo-noise sequence of bangs (hereinafter referred to as "bang"), which is widely used as pseudo-speech, pseudo-random numbers, etc. due to its irregularity, sharp autocorrelation, and other characteristics.
) is used.

23 converts the signal processed by the transmission circuit 6 into a transmission signal and PN
A first separation circuit 24 separates the transmission signal into a monitoring signal based on a pattern, and returns the speed of the transmission signal separated by the first separation circuit 23 to the original speed, and outputs the transmission signal via the line interface 5 to the transmission signal output terminal. 3 is a second speed conversion circuit that sends data to a communication line (not shown). Reference numeral 25 denotes a return circuit that returns the monitoring signal separated by the first separation circuit 23.

Reference numeral 26 denotes a third speed converting circuit which receives the received signal input from the communication line to the received signal input terminal 4 via the line interface 5 and converts the speed of the received signal to a higher speed one. 2T multiplexes the PN button of the monitoring signal returned by the return circuit 25 on the received signal whose speed has been converted by the third speed conversion circuit 26, and supplies the received signal to the receiving circuit T where fault detection is performed. It is a multiplex circuit.

28 is a second separation circuit that separates the signal processed by the receiving circuit 6 into a received signal and a monitoring signal, and 29 is a second separation circuit that converts the speed of the received signal separated by the second separation circuit 28 to the original signal. This is a fourth speed conversion circuit that returns the received signal to the same speed and sends it to the communication device through the received signal output terminal 2. 30 is the second separation circuit 28
The monitoring signal separated by the monitoring signal is compared with the PN pattern of the monitoring signal generated by the monitoring signal generation circuit 22 to detect a fault in the transmitting circuit 6 and the receiving circuit 7, and the fault detection result is outputted to the detection result output terminal 14. This is a check circuit.

Next, the operation will be explained. A transmission signal input to the transmission signal input terminal 1 of a communication device (not shown) is converted to a higher speed signal by a first speed conversion circuit 20. That is, the transfer rate of the transmission signal input to the transmission signal input terminal 1 is, for example, 1.54 of 9193 bits per frame (125 μS) as shown in FIG. 2(a).
The transfer rate is 4 Mbps, and this is converted by the first rate conversion circuit 20 to a transfer rate of 2.048 Mbps with 3 bits per frame as shown in FIG. 6). This speed conversion generates three empty bits per frame. The first multiplex circuit 21 inserts the PN pattern of the supervisory signal generated by the supervisory signal generating circuit 22 into the 63-Q vacant bit position.

The transmission signal, whose speed has been converted and the monitoring signal has been multiplexed, passes through the transmission circuit 6 and undergoes the necessary processing for transmission.
The signal is sent to the separation circuit 23. In the first separation circuit 23,
It is separated into a transmission signal and a monitoring signal, and the transmission signal is
A monitoring signal is sent to the loopback circuit 25. The second speed conversion circuit 24 performs speed conversion of the received transmission signal, and converts the received transmission signal to the original 1.544 Mb as shown in FIG.
The signal is returned to the ps frame configuration, electrically matched at the line interface 5, and transmitted through the transmission signal output terminal 3 to the communication line. Among them, the monitoring signal separated by the separation circuit 23 is sent to the loopback circuit 25 and looped back.

On the other hand, the received signal input from the communication line to the received signal input terminal 4 also has a frame structure of 1.544 Mbpa as shown in Figure 2), but after electrical matching is achieved at the line interface 5. , and is sent to the third speed conversion circuit 26 where it is speed converted into a signal having a frame structure of 2.048 Mbps as shown in FIG. The speed-converted signal is sent to the second multiplex circuit 2T, where the monitoring signal PN button returned by the return circuit 25 is multiplexed onto the 63 empty bits, and input to the receiver circuit T. . The receiving circuit T performs processing necessary for reception on the signal, and then sends it to the second separation circuit 28. Second separation circuit 28
separates the signal into a received signal and a monitoring signal, and sends the received signal to the fourth speed conversion circuit 29. Fourth speed conversion circuit 2
9 converts the speed of the received signal and returns it to the original 1.544 Mbps frame configuration shown in Figure 2 (false).
The received signal is sent to the communication device through the output terminal 2.

On the other hand, the monitoring signal separated by the second separation circuit 28 is sent to a check circuit 30 to check the PN pattern. That is, the check circuit 30 compares the PN button of the monitoring signal input to the second separation circuit 28 with the PN button of the monitoring signal generated by the monitoring signal generation circuit 22, and if the two are equal, it is determined that there is a failure. If there is no failure, it is determined that there is a failure, and the failure detection result is outputted to the detection result output terminal 14.

In the above embodiment, the frame structure of the transmitted signal and the received signal is the 1.544 Mbps frame structure shown in FIG. 2.048 M shown in Figure 2
bps frame configuration is used, but other frame configurations may be used.

Further, in the above embodiment, a case has been described in which a PN pattern is used as monitoring information for failure detection, but other types of monitoring information may be used, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, a monitoring signal is multiplexed on a transmission signal whose speed has been converted to a high speed, and is input to the transmission circuit where fault detection is performed, and the monitoring signal is separated from the signal output from the transmission circuit. multiplexing the looped back monitoring signal with a received signal whose speed has been converted to a high speed, inputting the looped back monitoring signal to a receiving circuit where fault detection is performed, and separating the monitoring signal from the signal output from the receiving circuit; This is compared with the monitoring signal multiplexed with the transmitting signal to detect a failure in the transmitting circuit and receiving circuit, so even if a received signal is present at the received signal input terminal, the transmitting circuit and receiving circuit The present invention has the effect of providing a fault detection device that can constantly detect faults in the transmitting circuit and receiving circuit while performing normal transmission and reception of transmitting and receiving signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a fault detection device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of frame structure conversion by speed conversion, and FIG. 3 is a block diagram showing a conventional fault detection device. be. 6 is a transmitting circuit, T is a receiving circuit, 20 is a first speed conversion circuit, 21 is a first multiplex circuit, 22 is a monitoring signal generation circuit,
23 is a first separation circuit, 24 is a second speed conversion circuit, 2
5 is a folding circuit, 26 is a third speed conversion circuit, 2T is a second multiplex circuit, 2B is a second separation circuit, 29 is a fourth speed conversion circuit, and 30 is a check circuit. In addition, the same symbols in the figures indicate the same or equivalent parts. (2 others) Chart procedural amendment (voluntary) 1. Relation of case description to case No. 7-325223 Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4゜ Representative Masato Zip code 105 Address 1-4-1-6 Nishi-Shinbashi, Minato-ku, Tokyo
Contents of the amendment (1) In the 11th line of page 3 of the specification, the phrase "road interface" is amended to read "line interface." (2) “Circuit interface” on page 3, line 12 of the specification
Correct that to "line interface." (3) Correct Figure 2 as shown in the attached sheet. 7. Document stating Figure 2 after the revised catalog of attached documents 1 Continuous kite Upper Figure

Claims (1)

[Claims] A first speed conversion circuit that converts the speed of a transmission signal of a communication device to a higher speed; and a transmission in which a monitoring signal is multiplexed on the transmission signal speed-converted by the first speed conversion circuit, and a failure is detected. a first multiplex circuit supplying the circuit;
a supervisory signal generating circuit that generates the supervisory signal to be multiplexed with the transmitting signal in a multiplex circuit; a first separating circuit that separates the signal output from the transmitting circuit into the transmitting signal and the supervisory signal; a second speed conversion circuit that returns the speed of the transmission signal separated by the first separation circuit to the speed of the transmission communication line; and a return of the monitoring signal separated by the first separation circuit. and a third circuit that converts the speed of the received signal received from the communication line to a higher speed.
a speed conversion circuit; and a second speed conversion circuit that multiplexes the received signal whose speed has been converted by the third speed conversion circuit with the monitoring signal returned by the return circuit, and supplies the received signal to the receiving circuit in which fault detection is performed. a multiplexing circuit; a second separation circuit that separates the signal output from the reception circuit into the reception signal and a monitoring signal; and a speed of the reception signal separated by the second separation circuit, the communication device a fourth speed conversion circuit that returns the speed to the speed of
A fault detection device comprising: a check circuit that compares the monitoring signal generated by the monitoring signal generation circuit and outputs a fault detection result.