JPH0318771B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a counter circuit in an information processing device having a plurality of counters.

BACKGROUND ART Conventionally, when configuring a plurality of counters in an information processing device, although the update cycle is generally sufficiently large compared to the machine cycle, the counted value is unique due to differences in update direction, addition/subtraction constant, and count cycle. It was necessary to prepare an update circuit for each update, which had the disadvantage of increasing the amount of hardware.

DISCLOSURE OF THE INVENTION It is an object of the present invention to configure a plurality of counters whose update period is sufficiently large with respect to a machine cycle, and to determine the counted value of the counter, the update direction unique to the counter, the addition/subtraction constant, and the To provide a counter circuit which gives a common scannable address to a count instruction pulse signal of a counter so that the counters can be commonly processed, and which enables updating with only one updating circuit.

Describing the structure of the present invention, the present invention provides an information processing device that has a plurality of counters and generates a plurality of pulse signals each having a period unique to the plurality of counters, The first one that addressably stores the value
a second storage means for addressably storing instruction information that determines a count direction and a count number specific to the counted value; and a second storage means that is scannable with respect to the first and second storage means. a plurality of holding means that are provided in one-to-one correspondence with the plurality of pulse signals and hold a first state when the corresponding pulse signals are applied; One of the plurality of holding means is selected based on the address sequentially output at a period equal to or shorter than the unique period, and after outputting the state of the selected holding means, a selection means for holding a second state, and a state of the holding means outputted from the selection means for determining the counted value in the first storage means specified by the address outputted from the addressing means; Said first
This counter circuit has updating means for updating the count according to an instruction from the second storage means when the state is indicated.

According to the present invention, even if there are multiple counters, only one update circuit can be used by storing the counted value, update direction, addition/subtraction constant, and count instruction signal of each counter in an addressable manner. By simply doing this, all counters can be updated, which has the effect of reducing the amount of hardware required.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described by way of examples with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the invention.
In FIG. 1, a register file 1 stores counted values of a plurality of counters. Signal lines 6 and 7 are the initial setting path and readout path of the register file 1, respectively. The signal line 8 connects the operation result output of the adder/subtractor 5 to the input end of the register file 1, and the signal line 9 connects the output of the register file 1 to the input end of the adder/subtracter 5. Part 2a of register file 2
2b stores an addition/subtraction constant corresponding to the counted value, and 1-bit information for determining the update direction corresponding to the counted value is stored in the part 2b. When the content of portion 2b is "0", the update direction is -, and when it is "1", the update direction is +. The signal line 10 is an initial setting path for the register file 2. Signal line 11 is part 2 of register file 2
The output terminal of b is connected to the adder/subtracter 5. Signal line 12
connects the output end of the portion 2a of the register file 2 to the adder/subtractor 5. The address generation circuit 3 is a counter circuit that scans in machine cycles, and supplies an address to the register file 1, 2 count instruction signal selection and holding circuit 4 through a signal line 13. The count instruction signal selection and holding circuit 4 holds the count instruction signal of the counter inputted through the signal line 14 until an address is specified through the signal line 13. The signal line 15 connects the output terminal of the count instruction signal selection and holding circuit 4 to the adder/subtractor 5.
It is connected to. The adder/subtractor 5 is connected to the signal line 9
When the signal input from the signal line 15 is "1", the input is calculated using the addition/subtraction constant specified by the input through the signal line 12 and the update direction specified by the input through the signal line 11, and the calculation result is calculated. Output to signal line 8. When the signal input from the signal line 15 is "0", the calculation result is outputted as is from the signal input to the signal line 9. The signal line 16 is connected to the register file 1,
This is an input line for a signal for setting an address in the address generation circuit 3 in order to initialize the address generation circuit 2.

Next, the operation shown in FIG. 1 will be explained. First, an address is given to the address generation circuit 3 through the signal line 16, and the register files 1 and 2 are initialized through the signal lines 6 and 10, respectively. After initial setting, the address generation circuit 3 scans in machine cycles,
Addresses are given to register files 1 and 2 and the count instruction signal selection and holding circuit 4 through the signal line 13, and the output of the addressed register file 1 is an instruction for the output of the register file 2 and the output of the count instruction signal selection and holding circuit 4. is calculated by the adder/subtractor 5 and stored in the register file 1 again. (This operation will be referred to as update operation hereinafter). For example, if there are three addresses 0, 1, and 2, if address 0 is updated in a certain machine cycle T ₀ , address 1 is updated in machine cycle T ₀ +1, address 2 is updated in T ₀ +2, and address 2 is updated in T ₀ +3. Then the update operation continues like address 0, and signal line 1
The counted value of register file 1 is counted only when 5 is "1". Therefore, a plurality of counters can be configured with a single update circuit regardless of differences in individual update conditions.

FIG. 2 is a detailed block diagram of the count instruction signal selection and holding circuit 4. FF40 to FF47 are flip-flops corresponding to words 0 to 7 of register files 1 and 2, and signal lines 140 to 147 shown by signal line 14 in FIG. 1 are input as set signals, respectively. Signal lines 140 to 147 are count pulse signals having a predetermined period as shown in FIG. Further, the output signals 410 to 417 of the decoder 401 are input to FF40 to FF47 as hold signals of one bit each, for example.
The FF45 is set by a count pulse signal with a period of 100T inputted through the signal line 145, and
If it is “0”, it is held and the signal line 415 is “1”
It works so that it stops holding when it reaches that point. The decoder 401 decodes the output of the address generation circuit 3 as shown in FIG. 4, and generates and outputs signal lines 410-417. Therefore, in the case of the signal line 415, it becomes "1" only when the output of the address generation circuit 3 is 5 _(H) . In addition, the output of the address generation circuit 3 is changed from 0 → 1 → 2 → according to the words of register files 1 and 2.
Since the machine clock scans in the order of 3→4→5→6→7→0→1→..., the signal line 415 becomes "1" in 8T cycles. selector 4
02 is the output signal 420-42 of FF40-FF47
7 is input, and according to the value of the address generation circuit 3, it is selectively output as shown in FIG. That is, in the case of the FF45, the selective output is performed only when the output of the address generation circuit 3 is 5 _(H) . (Output to signal line 15) As described above, the addition/subtraction constant of word 5 of register file 2 is set so that the counted value of word 5 of register file 1 is increased by +30 for each count instruction.
If the update direction is set, the operation is performed as shown in the time chart of FIG. 5, and the counter value A of word 5 of register file 1 is incremented by +30.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing details of the circuit 4, and FIGS. 3 to 5 are diagrams for explaining the operation of the circuit 4. 1...first storage means (register file),
2...Second storage means (register file), 3
...Means for giving an address (address generation circuit),
4... Count instruction signal selection and holding circuit, 5... Update circuit (adder/subtractor).

Claims (1)

[Scope of Claims] 1. In an information processing device that has a plurality of counters and generates a plurality of pulse signals each having a period unique to the plurality of counters, the counted value of each of the counters can be addressed. a first storage means for storing in the first and second storage means; a second storage means for storing in an addressable manner instruction information for determining a count direction and a count number specific to the counted value; addressing means for giving a scannable address to the plurality of pulse signals; and addressing means provided in one-to-one correspondence with the plurality of pulse signals, and when the corresponding pulse signal is applied, a first
a plurality of holding means for holding the state; and one of the plurality of holding means is selected based on the address sequentially output from the addressing means at a period equal to or shorter than the unique period; selecting means for causing the holding means to hold a second state after outputting the state of the selected holding means; and a count value in the first storage means specified by the address output from the addressing means. and updating means for updating the count according to an instruction from a second storage means when the state of the holding means output from the selection means indicates the first state.