JPS59200328A - Central processing unit incorporating data transfer circuit - Google Patents

Abstract

PURPOSE:To exclude a special pin which is used for control of data transfer and to obtain simple and miniature constitution of a data transfer circuit, by using a means for delivering address of both the transfer destination and the transferer of data, a means for counting the number of data transfer words, etc. CONSTITUTION:A means for delivering addresses of both the transfer destination and the transferer of data is provided together with a means for counting the number of data transfer words. For instance, the addresses of the transferer and transfer destination of data and the number of transfer words are written in the 1st and 2nd address generating parts 3 and 4 of a data transfer circuit part 2 as well as to a word number counter 6 by the program of a CPU part 1'. At the same time, a BUSY signal 10 is set at ''1'' together with the holding signal and a holding confirmation answer signal 11 of the part 1'. Then a DMAEN signal 12 is set at ''1'', and the output of the part 3 is enabled when an SELR signal 14 is set at ''1''. The signal 14 is delivered as the address of the transferer. When the signal 12 and an SELW signal 15 are set at ''1'', the address of transfer destination is delivered in the same way.

Description

[Detailed Description of the Invention] Flame LLL The present invention relates to a semiconductor circuit, and more specifically, to a semiconductor circuit that performs data transfer between an input/output device and a memory, and between memories, etc. in a microcomputer system. The present invention relates to a central processing unit with a built-in data transfer circuit for the purpose of processing.

Prior Art Conventionally, DMA (
A DMA controller is generally used for direct memory access (direct memory access) transfer, but in this case, a control signal line between the DMA controller and the CPU and a control signal line between the DMA controller and the data transfer element are required, and the circuit There was a problem that the configuration became complicated.

Purpose The present invention provides a simple circuit configuration in a digital circuit having an arithmetic unit, memory, I10 port, etc., and it is possible to omit bins for DMA control signals from the CPU.
The purpose is to provide an A transfer method to simplify and downsize the circuit.

11 The configuration of the present invention will be described below based on specific examples. FIG. 1 is a block diagram showing the internal configuration of a CPU 1 of the present invention incorporating a data transfer circuit, and FIG. 2 is a timing chart thereof.

The CPU 1 is a CPU section 1' having conventionally known arithmetic functions, etc.
In addition, a data transfer circuit section 2 is built-in. CPU1
is a general CP such as address output signal, data input/output signal, read/write signal, system clock input signal, etc.
Although it has a terminal for realizing the U function, terminals for, for example, a hold request signal and a hold acknowledgment signal for controlling bus occupancy during data transfer are omitted.

The data transfer circuit section 2 includes a first address generation section 3, a second address generation section 4. Data balance 51 word counter 6,
Timing creation circuit 7. It consists of a write signal generation circuit 8. The write signal generation circuit 8 is composed of an address decoder and a gate circuit, and decodes the address signal from the CPU section 1' and uses the first address generation section 3, the second address generation section 42, and the word counter 6 at the timing of the read/write signal 9. Generates a write signal for. That is, this allows the CPU
Desired data is set by the program from section 1'. The first address generating section 3 consists of a 16-bit counter and is used to set a data transfer source address. on the other hand,
The second address generating section 4 consists of a 16-bit register and is used to set a data transfer destination address. All outputs are three-state outputs, and the address signal 16 of the CPLI section 1'
It is connected to the AO to A+s terminals 17 of the CPU 1 together with the bits. The word counter 6 is for setting the number of words to be transferred, and is 1
A count is performed every time a word is transferred, and an end signal 13 is generated when the set number of words is completed. It is preferable that an up counter is used as the word counter 6, and the number of transferred words is set as a complement so that the end signal is generated when the counter reaches 0. ≠-The buffer 5 consists of an 8-bit register,
Both input and output are C
It is connected to the Do to D7 terminals 18 of PLI 1, and the output is a three-state output. The timing generation circuit 7 consists of a flip 70 block and a gate circuit, and receives a clock signal φ1 input from the system clock φ1 terminal 20 of the CPUI.
From this, φ22 times consisting of even-numbered pulses and φ33 times consisting of odd-numbered pulses are created. That is, a non-crossover clock φ2. whose repetition period is twice that of φ1. Create φ3 (see Figure 2). In addition, it is 111 I+ from when the number of words to be transferred is instructed by the write signal from the write signal generation circuit 8 until the end signal 13 is generated from the word number counter 6, and is ``0'' otherwise. A signal 10 is created.The BLISY signal 10 is connected to the hold signal terminal of the CPU section 1'.
When the USY signal is "1" and the hold confirmation response signal 11 from the CPU section 1' is also 1", the MAEN signal 12 becomes 11111, and the MAEN signal 12 is created.Furthermore, it becomes "1" at the rising edge of φ3, and the A 5ELW signal 15 which becomes "O" at the rising edge of φ3 and a 5ELR signal 14 by its inversion are created (see Figure 2).Also, when the DMAEN signal 12 is "0", the CPLI section 1' is read. /Write signal 9 is output and DMAEN signal is “1”, 5EL
A signal for connection to the R/W signal terminal 19 of the CPUI is created so that the R signal 14 is output.

Next, the data transfer operation in this embodiment will be explained. First, the initial value of the data transfer source address and the data transfer destination address are determined by the program.

The number of words to be transferred is determined by the first address generation unit 3. The second address generator 49 is written into the word counter 6. Since the write signal to the word counter 6 simultaneously sets the BUSY signal 10 to "1", the hold signal of the CPU section 1' becomes "1".
After that, the hold confirmation response signal 11 of the CPU section 1' becomes ll I I+, and the DMAEN signal 12 also becomes 1.
11 Becomes I+. DMAEN signal 12 is 1″ and 5
When the ELR signal 14 is 1'', the output of the first address generator 3 is enabled and CPLII is used as the transfer source address.
It is output to Ao to A+s terminals 17 of. Also, DMAEN
When the signal 12 is "1" and the 5ELW signal 15 is 1", the output of the second address generator 4 is enabled and is output to the AO to A+s terminals 17 of the CPU as a transfer destination address. The 5ELW signal 15 is a word counter. 6, and adds 1 to the first address generator 3 to update the transfer source address.During data transfer, the CPU 1
The 5ELR signal @14 is output to the R/W terminal 19 of the transfer source and is used to control the transfer source and transfer destination. That is, DMAEN signal 1
When 2 is 1111+ and 5ELR signal 14 is “1”, transfer data is transferred from the transfer source to CP (Do of l = D7 terminal 18
is taken into the data buffer 5 via DMAE.
N signal 12 is "1'° and 5ELR signal 14 power ("0
'', the data is output from the data buffer 5 to the Do-D7 terminals 18 of the CPU 1 and transmitted to the transfer destination.Word counter 6
When the end signal 13 is generated, the BUSY signal 10 becomes O.
11, and the first address generating section 3. Second address generator 4. The output of the data buffer 5 is disabled and the hold state of the CPU section 1' is released.

In this embodiment, the transfer destination address is fixed, but M2
If the address generating section 4 also uses a counter and counts up each time one word is transferred, the transfer destination address can be updated. That is, transfer between memories is also possible. It is also possible to transfer data from the I10 device controller to the memory by making the first address generation section 3 fixed and the second address generation section 4 updatable. If the memory address is set only in the upper 8 bits and the output of the word counter 6 is used as the lower 8 bits, the circuit becomes even simpler. In that case, for example, the word counter may count up from all zeros and generate an end signal after 256 words have been transferred.

Furthermore, in this embodiment, the CPU section 1' has a function of floating the address bus and data bus by means of a hold signal. However, even if it does not have a hold function, the ready signal will cause the CP to
The same data transfer function as in this embodiment can be achieved by setting the U section 1' in a waiting state and providing a switch for cutting off the open signal of 1'' of the DMAEN signal on the address output signal line from the CPU section 1'. It is possible to achieve this.

Effects According to the present invention, special bins for data transfer control, such as hold signals, hold acknowledgment signals, etc., can be omitted from the central processing unit.

In addition, since the transfer circuit is built into the CPU, there is no need for a special circuit configuration for data transfer in any digital circuit.Using this CPU simplifies circuit design and enables high-speed operation. data transfer becomes possible. Therefore, the mounting area can be reduced and the device can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of a CPU incorporating the data transfer circuit of the present invention, and FIG. 2 is a timing chart thereof. (Explanation of symbols) 1: CPU with built-in data transfer circuit 1': CPL1 section 2: Data transfer circuit section 3: First address generation section 4: Second address generation section 5: Data buffer 6: Word counter 7: Timing generation circuit 8: Write signal generation circuit patent applicant Rico Co., Ltd. - Nanano 1/

Claims (1)

[Claims] 1. A first address generation section for outputting a data transfer source address, a second address generation section for outputting a data transfer destination address, and a word counter for counting the number of data transfer words. and the first address generating section, the M
2, a write signal generation circuit for initializing the address generation unit and the word counter, a data buffer 1 for temporarily holding data for transfer, and a timing creation circuit for creating timing for data transfer. A central processing unit characterized by having a built-in central processing unit. 2. The central processing unit according to item 1 above, wherein the word counter is located in the first address generation section or the second address generation section.