JPH03188725A - Asynchronous signal transmission/reception circuit - Google Patents

Abstract

PURPOSE:To prevent a data transmission/reception error cause by the contention of both latch timings at a transmission side and a reception side by masking the latch timing at the transmission side in the vicinity of the latch timing of the reception side. CONSTITUTION:A reception side pulse generating section 2 generates a latch pulse 2 and sends it to a control section 4, generates a masking pulse designating the inhibiting period of a preset length over before and after the appearance period of the latch pulse 2 and sends it to a comparison section 3. The comparison section 3 sends a latch pulse 3 masking the latch pulse 1 at the transmission side designated by the masking pulse to the control section 4. The control section 4 latches an input data synchronously with the frame pulse 1 given from the transmission side by using the latch pulse 3 and reads the data to obtain an output data by latching the read data by using the latch pulse 2. Thus, the malfunction due to the contention of the latch pulse is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous signal transmitting and receiving circuit, and more particularly to an asynchronous signal transmitting and receiving circuit for transmitting and receiving data between digital signal processing circuits whose operation clocks are asynchronous with each other.

[Conventional technology]

This type of conventional asynchronous signal transmitting/receiving circuit latches and reads data on the transmitting side with a frame pulse synchronized with this, and latches and reads this read data with a frame pulse on the receiving side, so that the operating clocks are mutually controlled. Data is sent and received asynchronously from the sending side to the receiving side.

[Problem to be solved by the invention]

In this conventional asynchronous signal transmitting/receiving circuit, when the latch pulses on the transmitting side and the receiving side conflict, that is, when the latch timing on the receiving side fluctuates temporally in the vicinity of the latch timing on the transmitting side, the latch pulse on the receiving side Since data is read repeatedly or skipped, there is a problem that correct data transmission and reception cannot be performed.

[Means to solve the problem]

The circuit of the present invention includes a first pulse generator that outputs a first latch pulse for instructing the latch timing of the input data in response to a frame pulse and a clock pulse synchronized with the input data; Generation of a second pulse that outputs a second latch pulse that instructs the latch timing of output data in response to the frame pulse and the clock pulse, and a masking pulse that instructs the inhibit period set before and after the second latch pulse. a comparator unit that outputs a third latch pulse by masking the first latch pulse during the instruction period of the masking pulse; and a comparator unit that reads the input data at the timing of the third latch pulse and outputs the second latch pulse. and a control section that reads the output data at the timing of the latch pulse.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a signal timing diagram illustrating the operation of this embodiment.

The pulse generator 1 on the transmitting side generates a clock pulse (
1) and the frame pulse (1) obtained by dividing this,
A latch pulse (1) is generated and sent to the comparator 3. The pulse generator 2 on the receiving side generates the clock pulse (2) on the receiving side.
A latch pulse (2) is generated from the frame pulse (2) obtained by dividing the frequency of the latch pulse (2) and sent to the control unit 4, and an inhibition period of a preset length is set before and after the appearance period of the latch pulse (2). A commanding masking pulse is generated and sent to the comparator 3. The comparison unit 3 sends to the control unit 4 a latch pulse (3) that masks the pulse of the latch pulse (1) only for an inhibit period designated by the masking pulse.

The control unit 4 receives a frame pulse (1
) is latched with a latch pulse (3) and read, and this is latched with a latch pulse (2) to obtain output data. Even if latch pulse (1) and latch pulse (2) conflict, the comparator 3 selects latch pulse (1).
is masked, so malfunctions due to latch pulse competition are prevented.

〔Effect of the invention〕

As explained above, the present invention can prevent errors in data transmission and reception caused by conflicts between latch timings on both the transmitting side and the receiving side by masking the latch timing on the transmitting side in the vicinity of the latch timing on the receiving side. This has the effect that data can be transferred normally between asynchronous circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal timing diagram of the embodiment of the present invention. 1.2... Pulse generation section, 3... Comparison section, 4...
control section.

Claims (1)

[Claims] a first pulse generator that outputs a first latch pulse for instructing the latch timing of the input data in response to a frame pulse and a clock pulse synchronized with the input data; a second latch pulse that instructs the latch timing of output data, and a masking pulse that instructs a prohibition period set before and after the second latch pulse.
a pulse generator, a comparator that outputs a third latch pulse by masking the first latch pulse during the instruction period of the masking pulse, and reads the input data at the timing of the third latch pulse. An asynchronous signal transmitting/receiving circuit comprising: a control section that reads out the output data at the timing of the second latch pulse.