JPH03189768A - Fault simulation system for logic lsi - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testing technique for semiconductor integrated circuits and a technique that is particularly effective when applied to evaluating the failure coverage of logic test patterns of logic LSIs. For example, the present invention relates to a technique that can be effectively used to speed up the evaluation of test patterns in logic LSI failure simulation using a concurrent method.

[Prior Art] In order to detect a failure in a logic LSI, a method has been implemented in which a test pattern is input from an input bin while observing an output bin, and it is determined whether the output signal matches an expected value. However, as the scale of logic LSI increases, the amount of test patterns increases exponentially, and
% perfect fault discovery rate is becoming impossible due to time and cost considerations. Therefore, it became important to develop efficient test patterns, and failure simulation was developed to evaluate the test patterns.

Fault simulation for verifying logical operation in a logic circuit is performed by simulating a normal circuit that corresponds to an element model that constitutes a simulated logic circuit, and a faulty circuit that is assumed to be due to a single stuck-at fault, etc. This is to verify whether there are differences in signal values in the output of each circuit.

Conventionally, fault simulation methods include a parallel simulation method that simultaneously simulates a normal circuit and a faulty circuit corresponding to the width of one word of the computer executing the simulation, and a parallel simulation method that simulates the propagation of fault information based on the results of logical simulation. There are other methods of ento simulation, including concurrent simulation methods, and currently the concurrent method is the mainstream. Regarding the concurrent simulation method, please refer to November 3, 1972.
As described in the rLSI Handbook JP179 published by 0-day Ohm Co., Ltd., when the input or output of an element model in a simulated logic circuit differs from that of a normal circuit due to the influence of a fault, there is a method for identifying the fault. In this method, data and input/output values at that time are held in the form of a fault list, and the fault list is updated by performing simulations on both normal and faulty circuits.

In other words, as many faulty circuits as there are faulty models that exist in a logic circuit are considered, and the logical behavior of a normal circuit is simulated. At the same time, a test pattern is inserted to propagate information on signal values different from normal circuits to each faulty circuit. This method detects the difference in the output bins and evaluates the failure detection rate of the test pattern.

However, in the concurrent fault simulation described above, when both a normal circuit and a faulty circuit are simulated at the same time and the fault list is updated, information on signal values different from those in the normal circuit is propagated for each faulty circuit. Were you performing sequential logic simulations for all faulty circuits corresponding to the model?
As the scale of logic to be simulated increases, the number of faulty circuits increases significantly, resulting in an increase in memory capacity and calculation time for fault lists.

Therefore, the present applicant first developed a system for simulating the logical operation of a normal circuit corresponding to an element model constituting a simulated logic circuit and a faulty circuit assumed by a single stuck-at fault. By comparing and determining the states of faulty circuits in the model,
By integrating faulty circuits in the same state and maintaining the corresponding integrated identification data and input/output values, by propagating information on signal values different from those in the normal circuit to a predetermined logic path of the faulty circuit, the same state can be achieved. This reduces the memory capacity required for the fault list by integrating faulty circuits, and storing the corresponding fault list in one, reducing the memory capacity required for the fault list, and also storing faults in accordance with the number of integrated faulty circuits. We developed a method for reducing the number of calculations for circuit elements (hereinafter referred to as the convolution method) and applied for it in Japanese Patent Laid-Open No. 63-2.
04338).

[Problem that Gu δ Ming attempts to solve] The above convolution method can reduce the number of element operations of a faulty circuit by combining faulty circuits in the same state into one, but it When summarizing the faulty circuits, there is a problem that the number of comparisons and judgments of inputs and outputs between faulty circuits increases, and this judgment takes time.

The purpose of this invention is to simplify the comparison and judgment of the states of faulty circuits in fault simulation using the convolution method.
The purpose is to speed up the integration processing of faulty circuits in the same state and reduce the burden on the CPU.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, as shown in Figure 1, the input/output status Si of the faulty circuit, such as the input/output voltage value of the faulty circuit and the terminal position different from normal, is expressed as a numerical value (bit) for each element model, and the value (or This and the circuit identification data) are used as an address, and the identification data of the faulty circuit is placed in the area (ST) indicated by this address (fault circuit status table TT) or the index therein (address of the fault stack table ST). By setting and repeating this for the number of failed circuits, failed circuits in the same state are integrated.

Note that in FIG. 1, the terminals surrounded by mouths indicate terminals that are in a different state from the terminals in a normal circuit. In addition to "OJ" and "L", the input/output status for faulty circuit processing includes "output value undefined" and "output value O at high impedance" for output terminals.
, [Output value l at high impedance], [Output value undefined at high impedance], and for the input horn terminal, "
It is also possible to add "input value undefined" and convert them into numbers to use as addresses.

[Operation] According to the above-described means, when convolution is performed to combine faulty circuits in the same state into one, faulty circuits with the same numerical value (same address) become in the same state and are collected in one place.
Numerical values corresponding to input/output states can be integrated into memory as addresses without comparing and determining the states of faulty circuits, and processing speed can be improved.

[Example] FIG. 1 is a principle diagram of a convolution method for fault simulation according to this application, and FIG. 2 is a flowchart showing the procedure of convolution processing in the simulation system. The failure simulation system of this example is as follows:
Although not particularly shown, there is a central processing unit that functions as an instruction control system and an arithmetic execution system that executes arithmetic processing based on the control of the instruction control system, and a data storage means such as a semiconductor memory in which various data and programs are stored. It consists of a data processing system that includes The simulation method that can be executed with this system is to simulate both a normal circuit that corresponds to the element model that makes up the simulated logic circuit and a faulty circuit that is assumed to have a single stuck-at fault (not including two or more faults). The basic content is to propagate information on signal values different from normal circuits to each faulty circuit while simultaneously simulating the fault list and updating the fault list. Instead of performing sequential logic simulation using a given element model, faulty circuits in the same state are integrated, and the corresponding integrated identification data and input/output values are stored in a given memory area as a fault list. Information on signal values different from the normal circuit (faulty circuit)
is propagated to a predetermined logic circuit.

Specifically, as shown in FIG. 4, when a three-person AND gate circuit and a three-person OR gate circuit whose input is the output of the AND gate circuit are representative element models, three For an element model composed of a human-powered AND gate circuit, an AND gate circuit in which all three human-powered inputs are set to "1" is set as a normal circuit TA, and one input signal composed of a three-human-powered OR gate circuit is set as a normal circuit TA. The OR gate circuit in which is [1] and the other two inputs are rOJ is defined as a normal circuit TB. Then, for a normal circuit TA, a faulty circuit assumed due to a single stuck-at fault has three human forces a, b, c and an output d sequentially rOJ, rlJ
, rlJ, rOJ are the faulty circuits EAI, 3 manual a,
b, c and output d are sequentially rlJ, rOJ, rN,
There are three types of faulty circuits EA2 and EA3 in which the human power a, b, c and output d are sequentially defined as rOJ, rtJ, rlJ, rOJ, and rOJ. In connection with the normal circuit TA, the faulty circuits on the other normal circuit TB side are connected to each of the faulty circuits EAI, EA2 . EA3
and three failure circuits EB that are individually related in an l-to-l correspondence.
I, EB2. EB3 is considered, but since they are faulty circuits in the same state with the same input and output values, they are integrated into one faulty circuit UEB.

Information on signal values different from those of the normal circuit, that is, data of the faulty circuit, is stored in a data storage means such as a semiconductor memory included in the data processing system for the simulation for each faulty circuit (if integrated, it is stored as one group). ) The retained information is retained as a failure list, but the retained information includes, but is not particularly limited to, failure circuit identification data for identifying individual failure circuits, and terminal identification data for identifying the positions of terminals in different states from normal circuits. , propagation data corresponding to values at terminals in different states from normal circuits, and integrated identification data for identifying integrated faulty circuits, integrated group names, etc.

As shown in Figure 2, the flow of the hydraulic fault simulation process is to first restore the input signal state changes in the normal circuit (step S1) in order to obtain the changes in the normal circuit. to change the input state of the normal circuit (step S2), perform a logical operation on the normal circuit (step S3), and then register the value when there is a change in the output signal of the normal circuit (step S4). . Next, it is determined whether there is a faulty circuit corresponding to the normal circuit (step S5), and if there is no faulty circuit, the process returns to step Sl and a normal circuit of another element model (logic circuit) is determined. Perform the above processing for .

When it is determined in step S5 that a faulty circuit exists, in order to obtain changes in a predetermined faulty circuit, the process moves to step S6 to first read the state change of the input signal in the faulty circuit and then based on the change in the state of the input signal in the faulty circuit. to change the state of the faulty circuit (step S7), and integrate faulty circuits in the same state, or merge faulty circuits that were integrated in the previous process but whose states are no longer the same due to the current change in the input signal. An integration/separation process (step S8) is performed to separate the data from the integrated group.

After that, when a logical operation is performed on the faulty circuit and a change occurs in the output signal of the faulty circuit, the value is registered (step S
9, 5IO) After that, the process returns to step S1 and the above process is repeated for the next logic circuit.

FIG. 3 shows the specific procedure of the fault circuit integration/separation processing (step S8) in the processing flow of the fault simulation. That is, first, the input/output state of the faulty circuit is digitized (step 581), and the faulty circuit state table TT is searched using this value as an address. If the faulty circuit stack table pointer Psi is not included in the table, a new faulty circuit stack is created. After setting the table point Psi in the faulty circuit state table, the identification data fi of the faulty circuit is added to the faulty circuit stack table ST pointed to by the new pointer. This makes it possible to integrate and separate faulty circuits in the same state at high speed without comparing their states.

After updating the stack table, it is determined whether there are any unprocessed faulty circuits (step 583). If there are, the process returns to step S81; if there are none, the process moves to step S9.

In the above embodiment, the identification data of the faulty circuit is registered in the faulty circuit stack table, but input/output values (failure status) may also be registered in addition to the identification data.

According to the above example, if the average element model is 2 people with 1 output, the number of states to be compared is 8, and the average number of faulty circuits when different from a normal circuit is 10, integration and separation of faulty circuits Since it is no longer necessary to compare the states of faulty circuits, it is expected that the CPU time will be saved four times. Also, during fault simulation, integration and separation processing of faulty circuits is performed in two steps.
If it occupies 0%, a total CPU time reduction of 15% is expected. Furthermore, since the input/output status of the faulty circuit is digitized and used as an address, calculation results can be obtained using a look-up table method.

As explained above, in the above embodiment, the input/output status of the faulty circuit, such as the input/output voltage value of the faulty circuit and the terminal position different from normal, is expressed as a numerical value (bit), and that value is used as an address. By setting the identification data of the faulty circuit in the area (ST) indicated by the location (fault circuit status table TT) or the index therein (address of the fault stack table ST), and repeating this for the number of faulty circuits, Since faulty circuits in the same state are integrated, when faulty circuits in the same state are combined into one, faulty circuits with the same numerical value (address) will be in the same state and collected in one place, so the state of the faulty circuit will be Since the numerical values corresponding to the input/output states can be integrated into the memory as addresses without comparing and determining the input/output states, processing speed can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiments, the normal circuit and the faulty circuit have been described as an AND gate circuit and an OR gate circuit to simplify the explanation, but the circuits or elements can be changed as appropriate. Furthermore, in the above embodiment, a faulty circuit assumed to be caused by a single stuck-at fault with respect to a normal circuit was considered, but the faulty circuit or fault model is not limited to this, and other fault models such as multiple stuck-at faults may be adopted. You can also do that.

In the above explanation, the invention made by the present inventor was mainly applied to failure simulation of the current method, which is the background field of application, but the present invention is not limited to this, and the invention It can also be applied to simulations.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a system that simulates the logical operation of a normal circuit that corresponds to an element model constituting a simulated logic circuit and a faulty circuit that is set correspondingly, the state comparison and judgment of the faulty circuit is simplified and the same state is It is possible to speed up the integration processing of faulty circuits and reduce the load on the CPU.

[Brief explanation of drawings]

@Figure 1 is a principle diagram of the convolution method for fault simulation according to the present invention, Figure 2 is a flowchart showing the procedure of convolution processing in the simulation system, and Figure 3 is a diagram showing the integration of faulty circuits in the flow of Figure 2. FIG. 4 is a flowchart showing the specific steps of separation processing, and is an explanatory diagram showing the principle of faulty circuit integration processing using the convolution method. T...Normal circuit, f, ~f,...Faulty circuit, T
T: Faulty circuit status table, ST: Faulty circuit stack table. ：Yelm・Figure 2 Figure 6 Nu, Puff'S7, C so7-Tesof'59/-1

Claims (1)

[Claims] 1. In a system for simulating the logical operation of a normal circuit corresponding to an element model constituting a simulated logic circuit and a faulty circuit set correspondingly, By converting the state into a numerical value and storing the identification data of the faulty circuit in memory using this as an address, faulty circuits in the same state are integrated, and the simulation is performed while holding the corresponding integrated identification data and input/output values. A logic LSI characterized by
failure simulation system. 2. The logic LSI according to claim 1, wherein the identification data of the failed circuit is stored in a memory area indicated by a pointer in a table indicated by the address.
failure simulation system. 3. The logic LSI failure simulation according to claim 1 or 2, wherein the process of integrating the faulty circuits in the same state includes a process of separating the previously integrated faulty circuits. system.