JPH03189850A - Data processor - Google Patents

Abstract

PURPOSE:To shorten transfer time by interposing a data working device between a bus and a memory receiving data transfer, and performing the data transfer from a memory on one side to the memory on the other side with a DMAC (direct memory access controller) as working data at the data working device. CONSTITUTION:When the request of DMA transfer from the memory 13 to the CPU 11 is issued, it is judged whether or not the working request of the data to be transferred is issued from the memory 13. When the working request is issued, a control signal to supply an instruction for the working and the working method of the data is outputted form the CPU 11 to a controller 18, and a data working unit 19 is activated. Meanwhile, the DMAC 12 takes out the data in the memory 13 to be transferred via the bus 15, and the data working device 16 performs the working of the data, and transfers it to the memory 14. In such a way, the transfer time when performing DMAC transfer in which the working of the data is required is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device used in personal computers, engineering workstations, and the like.

BACKGROUND ART Conventionally, as shown in FIG. 4, this type of device is a central processing unit (hereinafter abbreviated as CPU) that processes data, accesses data, and controls various other devices such as 10 and LSI.
1, a direct memory access controller (hereinafter abbreviated as DMAC) 2, which transfers data from one memory to another independently of the CPU, and a direct memory access controller (hereinafter abbreviated as DMAC) 2, which stores data from various masks such as the CPU and LSI. Or multiple memories 3 and 4 to output, these CPUI, DM
It consisted of a bus 5 to which an AC 2, memories 3, 4, etc. were coupled, and served as a path for data, control signals, etc.

Data is transferred from memory 3 to memory 4 by program transfer via CPUI and DMAC without via CPU1.
2 DMA transfer is now possible. DM
In the case of A transfer, when the data stored in the memory lJ3 requires processing such as reversing the focus or exchanging the upper and lower bytes, conventionally, the data is processed by the CPU 1 and then transferred to the υ memory by the DMCA 2. It was transferred to 4. Furthermore, in the case of program transfer, the CPU 1 processes data in the memory 3 and directly transfers it to the memory 4.

Regarding such MA transfer, Japanese Patent Application Laid-Open No. 58-8336
It is stated in the publication number etc.

Problems to be Solved by the Invention However, with this configuration, there is a problem in that it takes a long time to perform DMA transfer. This is because when transferring data in the memory 3, the CPU must take out the data from the memory 3, process the data inside the CPU, and then write it into the memory 4. Originally, DMA transfer was performed by CPU
The purpose is to directly transfer data from a certain area of memory to another memory without going through the CPU, based on commands from the CPU.
Because the data had to go through the PU once, the transfer time took longer.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a data processing device that can shorten the transfer time in the case of DMA transfer that requires data processing.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has a configuration in which a data processing device is interposed between a bus and a memory that receives data transfer.

Effects of the present invention With the above-described configuration, when data is transferred from one memory to another memory by DMA, the data processing can be performed by the CPU while the data is being transferred to the data processing device. It becomes possible.

Embodiment FIG. 1 shows a schematic configuration of a data processing apparatus according to an embodiment of the present invention. 11 is a CPU that processes data through various calculations, accesses data for reading and writing, and controls various I10, LSI, etc.;
12 is a CPU that transfers data between memories.
13 is a memory that stores data before being transferred; 14 is a memory that receives data after processing it from the memory 13; 15 is a path for control signals, etc.; CPU II, DMAC 12, memory 1
3. A bus that connects 14 and other controllers (not shown) to exchange data or signals; 16 a data processing bus that is connected between the bus 15 and the memory 14 that receives data transfer; and 16 a data processing bus that processes data; It is a device.

FIG. 2 shows details of this data processing device 16. 17 is an input buffer that temporarily stores the data transferred via the bus 15; 18 is a controller that controls the data processing unit 19 according to instructions from the CPU II such as whether or not to process and the type of processing; and 19 is an input buffer that follows instructions from the controller 18. A processing unit extracts and processes byte worth of data from 17, and an output buffer temporarily stores the processed data in memory 14.

The operation of the data processing apparatus configured as described above will be explained below with reference to the flowchart shown in FIG.

The memory 13 stores data that is desired to be transferred to the memory 14 after being processed. First, from memory 13 to C
When there is a request for DMA transfer to PUII (step 21)
, a command to request the start of transfer is issued from the CPU II to the DMAC 12 (step 22), and when the DMAC 12 accepts the command, the CPU 11 selects the start address that indicates which area of the memory 13 to transfer data, and from that start address. The offset value of is passed to DMACI2 (step 23). Then, it is determined whether or not there is a data processing request from the memory 13 for the data to be transferred (step 24), and if there is a processing request, the CP
A control signal is output from U11 to the controller 18 of the data processing device 16 for processing the data and giving instructions on how to process the data (step 25).
8 Turn on the hatter processing unit 19 (Step 2
6).

On the other hand, the DMAC 12 retrieves the data from the memory 13 to be transferred via the bus 15 (step 27), and the data processing device 16 processes the retrieved data (step 27).
Step 28). The data is extracted until the input buffer 17 of the data processing device 16 is almost full, and after being sequentially processed by the data processing unit 19, it is passed to the output buffer and transferred to the memory I4 (29).

In the case of normal DMA transfer in which there is no data processing request, it is determined in step 24 that there is no processing request, and the data is extracted from the memo January 3 in step 29 and transferred to the memory 14 as is in step 29. In this case, CPU11
Since no control signal is output from the controller 18 to the controller 18 of the data processing device 16, the input bag buffer 7, the data processing unit 19, and the output cover sofa 20 function as mere buffers.

In the embodiment described above, data is transferred from memory 13 to memory 14, but as shown in FIG. By interposing the , data can be transferred not only from the memory 13 to the memory 14 but also from the memory 14 to the memory 13.

Effects of the Invention As is clear from the above description, the present invention provides a data processing device that is interposed between a bus and a memory receiving data transfer, thereby improving DMA transfer from one memory to another memory. Since the data processing device processes the data without the CPU, the data can be transferred while the data is being processed, and the transfer time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a data processing apparatus according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of a data processing apparatus according to an embodiment of the present invention, and FIG. 3 is a schematic block diagram of a data processing apparatus according to an embodiment of the present invention. FIG. 4 is a schematic block diagram showing another embodiment of the present invention, and FIG. 5 is a schematic block diagram showing an example of a conventional data processing device. 11... Central processing unit (CPU), 12... Direct memory access controller (DMAC), 13
14...Memory, 15...Bus, 16...Data processing device, 17...Input cover, 18...Controller, 19...Data processing unit, addition...Output buffer.

Claims (1)

[Claims] a central processing unit, a plurality of memories, and a direct memory access controller coupled to each other via a bus; and a data processing device connected between the bus and the memory receiving data transfer, the direct memory access A data processing device characterized in that a controller transfers data from one memory to another memory while the data processing device processes the data.