JPH03192593A - Serial transmission fifo circuit - Google Patents

Abstract

PURPOSE:To easily cope even with the time interval outputting data and the time alteration of untill writing by setting the alteration of setting value to a control circuit part generating writing request i.e. an arbitrary number of empty data FIFO register. CONSTITUTION:At the state which the data are housed to the FIFO registers 1-3, as long as the write requiring signal line 15 is made active every time the data is transmitted from a transmission shift register 4, the registers 1-3 successively become empty and FIFO register status lines 11-13 become the active state. Hereupon at the system needed to make the signal line 15 in active state,the register 1 is previously set to the relevant bit of selective register 5 so that the output of 2 inputs AND 6-8 become active state. In such a manner, by the value set to the register 5 and with the arbitrary number of the empty data FIFO register, the writing requirement is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial transmission FIFO circuit, and more particularly to a serial transmission FIFO circuit for a communication control device connected to an external host processor.

[Conventional technology]

Conventionally, serial transmission FI in such a communication control device
The FO circuit is configured using a plurality of FIFO registers and a transmission shift register.

Figure 2 shows an example of such a conventional serial transmission FIF.
FIG. 3 is a configuration diagram of an O circuit.

As shown in Fig. 2, F in the conventional communication control device is
The IFO circuit has FIFO registers 1 to 3 that store parallel data written from outside the communication control device (not shown), converts the parallel data from the FIFO register 3 into serial data, and connects the serial data line 14.
It is equipped with a transmission shift register 4 for sending data to the FIFO register 1, and a data bus 10 for writing parallel data to the FIFO register 1, and the output of the write request signal line 15 is transmitted to the FIFO register 1.
This indicates that O register 3 is empty and ready for writing to FIFO registers 1, 2, and 3.

In such a FIFO circuit, FIFO register 3 is in an empty state (at this time, FIFO register 1 is
, 2 are also empty), a request is made to write parallel data to FIFO register 3. In such a configuration, the data stored in the transmission shift register 4 is transmitted, and before a transmission underrun condition (a condition in which there is no transmission data and the serial data is cut off midway) occurs, the parallel FIG. 2 is a configuration diagram of an FO circuit for writing data.

As shown in FIG. 3, this FIFO circuit is a transmitting circuit section in a communication control device, similar to the conventional example described above, and is
IFO registers 1 to 3, transmission shift register 4,
Data bus 10 is the same as the circuit shown in FIG. In this example, when FIFO register 2 becomes empty and the write request signal line 15 outputs a signal, it indicates that FIFO registers 1 and 2 are ready for writing. That is,
When FIFO register 2 becomes empty, FIFO register 2
requests to write parallel data.

This configuration is suitable when the data stored in the transmission shift register 4 and the FIFO register 3 is transmitted and parallel data can be written from outside the communication control device before a transmission underrun condition occurs.

[Problem to be solved by the invention]

The conventional serial transmission FIFO circuit described above activates the write request signal when the number of empty FIFO registers reaches a specified value of 3 or 2.

However, if the transmission rate changes and the time interval for outputting from the FIFO circuit changes, or if the time from outputting the write request signal to writing to the FIFO circuit changes, the control circuit section that generates the write request may change. The disadvantage is that it requires changes and is not flexible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a serial transmission FIFO circuit that can easily cope with changes in the time interval at which data is output or the time until data is written due to changes in the transmission rate.

[Means to solve the problem]

The serial transmission FIFO circuit of the present invention is provided in a communication control device that performs transmission and reception operations under control from an external host processor via a data bus, and the serial transmission FIFO circuit receives parallel data from the external host processor. a plurality of FIFO registers that store data in the order of transmission operations, a transmission shift register that transmits data from the FIFO registers, and a control register that is connected to the data bus and that sets predetermined values to control write requests. and a write request generation circuit that generates a write request based on the contents of the control register and information on vacancies and occupancies of the plurality of FIFO registers.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Figure 1 shows an FIF for serial transmission showing one embodiment of the present invention.
FIG. 3 is a configuration diagram of an O circuit.

As shown in FIG. 1, this embodiment shows a part of a communication control device that performs transmission and reception operations under the control of an external host processor (not shown). FIFO registers 1 to 3 that store received parallel data in the order of transmission operations, a selection register 5 that is connected to the data bus 10 and that controls the output of a write request to the serial transmission FIFO circuit, and a selection register. 5 contents and FI
Two-man AND6-8 for generating a write request to the FIFO circuit based on the free information of FO registers 1-3
It also has a write request generation circuit consisting of a three-man OR9.

That is, in this embodiment, a selection register 5 is used as a control register for controlling the output of a write request signal;
Two-person power A to select one of three types of writing requests
NDs 6 to 8 and a three-manpower OR 9 for combining three types of write requests into one are provided, and a write request signal line 15 requests writing of data to the FIFO registers 1 to 3. Note that 11 to 13 are FIFO registers 1 to 3, respectively.
FIFO register status line indicating that the FIFO register is empty.

First, when data is stored in FIFO registers 1 to 3 and data is transmitted from transmission shift register 4, FIFO register 1 becomes empty due to FIFO operation, and as a result, FIFO register status line 11 becomes active. become.

Here, in a system where it is necessary to activate the write request signal line 15 at this point in order to prevent a transmission underrun state due to reasons such as a high transmission rate, the output of the two-man AND 6 should be activated. A bit of the selection register 5 which is an input to the two-man AND 6 is set to "1" in advance.

Next, if the write request signal line 15 is not activated, no new parallel data will be written. Therefore, when data is transmitted from transmission shift register 4, FIFO register 1 is followed by FIFO register 2.
is also empty and the FIFO register status line 12 becomes active. Here, in a system where it is necessary to activate the write request signal line 15, the two-man power AND
"1pa" is set in advance to the bit of the selection register 5 which is the input to D7.

Furthermore, if a write request is not required yet, when the data is transmitted from the transmission shift register 4, the
Following register 2, FIFO register 3 is also emptied, and F
Activate IFO register status line 13. Therefore, the selection register 5 becomes a two-man AND80 input.
By setting the bit ``1'' in advance, the write request signal line 15 becomes active.

As described above, depending on the value set in the selection register 5, a write request can be generated for any number of empty FIFO registers. That is, F for serial transmission
FI for serial transmission of write request signal to engineering FO circuit
Instead of a fixed amount of empty data in the FO circuit, any amount can be generated.

〔Effect of the invention〕

As explained above, the serial transmission FIFO of the present invention
The circuit can generate a write request by changing the setting value to the control circuit section that generates the write request, that is, by setting an arbitrary number of empty FIFO registers, so that the transmission rate does not change. TeFIF
It is possible to deal with both cases where the time interval output from the O circuit changes and cases where the time from outputting the write request signal to writing to the FIFO circuit changes without changing the hardware. It has the effect of being removed.

[Brief explanation of drawings]

Figure 1 shows an FIF for serial transmission showing one embodiment of the present invention.
2 and 3 are block diagrams of a serial transmission FIFO circuit showing one conventional example and another example, respectively. 1 to 3... FIFO register, 4...
Transmission shift register, 5...Selection register, 6
~8...2-manpower AND, 9...3-manpower 0R110...Data bus, 11-13...
...F engineering FO register status line, 14...
...Serial data line, 15...Write request signal line.

Claims (2)

[Claims] (1) In a serial transmission FIFO circuit provided in a communication control device that performs transmission and reception operations under control via a data bus from an external host processor, parallel data from the external host processor is stored in the order of transmission operations. a plurality of FIFO registers, and the F
a transmission shift register that sends data from the IFO register; a control register that is connected to the data bus and sets a predetermined value to control write requests; 1. A FIFO circuit for serial transmission, comprising: a write request generation circuit that generates a write request based on free/full information. (2) The serial transmission FIFO circuit according to claim (1), wherein the write request generation circuit is constituted by a plurality of AND circuits and an OR circuit that takes the logical sum of the outputs of the plurality of AND circuits. Trusted FIFO circuit.