JPH023344B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character buffer type line adapter, and more particularly to a bit buffer circuit that exhibits great performance when used on a high-speed line.

As shown in Figure 1, the communication control unit LC receives transmission data from the data processing unit PU, and the line adapter LA decomposes it into bit serial data and sends it out to the line. If the part LC receives a special transmission character,
Transmission processing for that character may temporarily take a long time. For example, when receiving a DLE code in transparent transmission
This is the case when adding a DLE or generating a control field when receiving an address character in high data link control (HDLC) mode.

Even in such a case, the communication control unit is configured so that the next character can be transmitted in time for the transmission speed of the line.
Possible options include shortening the character processing time of the LC, or providing multiple character buffers in the line adapter.

However, the former method has the disadvantage that when the line transmission speed is high, it becomes difficult to perform all character processing in the communication control unit within one character transmission time, and the latter method has the disadvantage that the line adapter circuit There were growing shortcomings.

The present invention has been made in order to eliminate the above-mentioned disadvantages inherent in the conventional technology, and therefore, an object of the present invention is to provide a line adapter and a line adapter that alleviate the temporary peak value of character processing time of a communication control unit. The purpose of the present invention is to provide a new line adapter that can reduce the amount of hardware compared to a multiple character buffer system.

The above object of the present invention is to provide a buffer register for temporarily accumulating transmission characters from a communication control section, a shift register for decomposing the transmission characters into bit serials, and controlling the operations of these various registers. A first-in-first-outshift memory is provided at a subsequent stage of the shift register of the line adapter having a transmission control circuit that controls input/output operations, and transmission data from the communication control section is sequentially transferred to the first-in-first-outshift memory. This is achieved by adopting a method of transmitting the contents of the first-in-first-outshift memory to the line at the bit transmission rate of the line while accumulating the data. It can be relaxed.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the transmission character from the communication control unit LC is received by the transmission buffer register BFR, then sent to the shift register SFR, and decomposed into bit serial data. and is sent to the first-in-first-outshift memory FIFO. As shown in FIG. 3, the transmission data stored in memory 1 of the first-in-first-outshift memory FIFO waits until memory 2 of the first-in-first-outshift memory becomes "empty".
It is moved to memory 2 of the first-in-first-outshift memory. Thereafter, this transmission data is moved toward memory n of the first-in-first-outshift memory by a similar operation.

That is, the first-in-first-outshift memory FIFO outputs a data transfer permission signal to the transmission control circuit CNT if there is no data in the memory 1 of the first-in-first-outshift memory FIFO. Upon receiving the signal, the transmission control circuit CNT shifts the first-in-first-out shift memory from the shift register SFR.
Outputs the signal to transfer to FIFO and transfers the data.

On the other hand, the contents of the first-in-first-outshift memory FIFO are transmitted to the line at a timing synchronized with the bit transmission rate of the line under the control of the transmission control circuit CNT. Normally, the shift speed of the first-in-first-outshift memory is faster than the bit transmission speed of the line, so the transmitted data is sequentially stored in the first-in-first-outshift memory, and finally the first-in-first-outshift memory There are cases where the "empty" state disappears. In this case, the transmission control circuit CNT detects this state and transfers data from shift register SFR to first-in-first-out shift memory until it becomes "empty".
Prohibits transfer of transmit data to FIFO. and,
If the shift register SFR becomes unable to receive the next transmission data, the buffer register
Transfer from BFR to shift register SFR is prohibited, and furthermore, transfer of transmission data from communication control unit LC is also temporarily stopped.

In addition, even if the transmission of transmission characters from the communication control unit LC is temporarily interrupted due to special character processing in the communication control unit LC, the first-in-first-outshift memory FIFO on the line Accumulated transmission data is transmitted correctly.

The bit capacity of the first-in-first-outshift memory FIFO may be appropriately determined depending on the difference between the bit transmission speed of the line and the processing speed of the communication control unit LC.

As explained above, according to the line adapter of the present invention, the temporary peak value of the character processing time of the communication control unit can be alleviated, and the hardware In addition, since the first-in-first-outshift memory can use a commercially available LSI, the circuit configuration becomes simpler.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a general data communication system, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the configuration of a first-in-first-outshift memory. PU...Data processing unit, LC...Communication control unit, LA
…line adapter, BFR…transmission character buffer register, SFR…shift register that decomposes the transmission character into bit serial, FIFO…first-in-first-outshift memory,
CNT...Transmission control circuit.

Claims (1)

[Claims] 1. A buffer register that temporarily stores the transmission character from the communication control unit, a shift register that decomposes the transmission character into bit serial, a first-in-first-outshift memory, and the operation of each of the above registers and shift memory. and a transmission control circuit that controls input/output operations with the communication control section, and decomposes the transmission character from the communication control section into bit serial data in the shift register and stores it in the first-in-first-outshift memory. The contents of the first-in-first-outshift memory are sent to the line at the bit transmission rate of the line while being accumulated sequentially, and when the first-in-first-outshift memory becomes "full", the first-in-first-outshift memory is transferred from the shift register. - Temporarily suspends the transfer of transmitted data bits to the first-in-first outshift memory, and
A line adapter characterized in that if a free area becomes available in an outshift memory, the transmission data bits are transferred again and data transmission is performed.