JPH03192594A - Mos dynamic memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] This invention is a one-transistor type MOS dynamic RAM.
By compensating for the word line signal delay,
The present invention relates to a MOS dynamic memory that can obtain large signals at high speed.

Generally, in a one-transistor type MOS dynamic RAM, the presence or absence of charge accumulated in the MOS capacitor corresponds to binary information of 0° and 1°.Then, the transfer gate is turned on and the charge is stored in the MOS capacitor. Transfers the generated charge to the bit line. At this time, the sense amplifier circuit detects minute voltage changes that occur on the bit line depending on the presence or absence of charge. Note that since the bit lines and the word lines constituting the transfer gates are usually arranged in a matrix in the X and Y directions, what material they are made of is important in configuring the memory array.

FIG. 1 is a block diagram showing a memory array of a conventional MOS dynamic memory. (1) is a memory cell arranged in a matrix on the left and right sides, and a detailed cross section thereof is shown in FIG. (2) is a sense amplifier circuit provided for each row of memory cells (1) arranged in a matrix, and (3) is a sense amplifier circuit provided for each row of this memory cell (1) and on the left and right sides of the sense amplifier circuit. Dummy cells (4) are provided for each row of memory cells (1) and dummy cells (3), respectively.
Sense amplifier circuit (2) Bit line pairs arranged on the left and right sides respectively, (5) word lines arranged for each column of memory cells (1) on the left and right sides, (6)
are the dummy word lines placed in the left and right dummy cells (3), respectively, and (8) is the voltage VDD connected to the left and right memory cells (1) and dummy cells (3).
power line, (7) is the left and right dummy cell (3)
φP times the signal is sent to the -P line.

Note that the memory cell (1) shown in FIG. 2 is connected to the bit line (4).
+ is composed of an N diffusion region, and the word line (5) is composed of a metal line such as aluminum, where (9) is the first polysilicon of the memory capacitor counter electrode, the side is the gate oxide film, and (111 is the second polysilicon of the transfer gate, and @ is the thick field oxide film separating the memory cells from each other.

Further, FIG. 3 is a configuration diagram showing a memory array of another conventional MOS dynamic memory. Reference numeral 03 denotes memory cells arranged in a matrix on the left and right sides, and a detailed cross section thereof is shown in FIG. The memory cell shown in FIG. 4 (13 indicates a case where the bit line (4) is made of a metal line such as aluminum, and the word line (5) is made of second polysilicon.

Next, the operation of the MOS dynamic memory shown in FIGS. 1 and 3 will be briefly explained.

First, for example, when one of the left word lines (5) is selected, the right dummy word line (6
) is selected. Therefore, the corresponding left bit line (
The signal charge is transferred to the right bit line (4) corresponding to 4), and the minute potential difference generated at this time is detected and amplified by the sense amplifier circuit (2).

However, conventional MOS dynamic memory t!
In the MOS dynamic memory shown in FIG. 1, the transfer gate has a time balancing structure, so the gate length fluctuates greatly. Further, in the MOS dynamic memory shown in FIG. 3, the transfer gate is self-aligned, but due to the large resistance component of polysilicon, the RC component becomes large, making it unsuitable for high-speed operation. Furthermore, word line division performed to reduce the RC component requires an extra circuit, resulting in an increase in chip size.

Therefore, an object of the present invention is to provide a MOS dynamic memory that can compensate for delays in word line signals and transfer memory information to bit lines at high speed.

In order to achieve such an object, the present invention provides a decoder at one end of the word line for selectively driving the word line, which is connected to the other end of the word line arranged in the corresponding column, and is connected to the other end of the word line arranged in the corresponding column. One electrode of the memory capacitor of the memory cell arranged in a column is discharged when the potential of the word line arranged in the corresponding column changes from a low level to a high level, and while the word line is selectively driven. This means that a cell counter electrode control circuit for charging the battery is arranged in each column. This will be explained in detail below using examples.

FIG. 5 is a block diagram showing an embodiment of a MOS dynamic memory according to the present invention. -As an example.

A case is shown in which the memory cell (1) shown in FIG. 4 is used.

In the same figure, En collects a word line signal formed of polysilicon, and the detailed circuit is shown in Figure 6.
Opposite electrode (151) of the memory container formed of polysilicon
(See FIG. 7) is a counter electrode control circuit for discharging.

In the counter electrode control circuit shown in FIG. 6, (16a) is the word line (5) arranged in the corresponding column.
The gate electrode is connected to the terminal end of the line, one electrode is connected to the discharge end of one electrode (counter electrode) of the memory capacitor arranged in the corresponding column, and the other electrode is connected to the φG line. A first MOS transistor (16b) is connected between the gate electrode of the first MoS transistor and the terminal end of the word line (5) arranged in the corresponding column, and the gate electrode is connected to the power supply line (8). the second MO3I- connected to
This transistor is used to separate the capacitance at the gate electrode of the first MOS transistor (16a) from the capacitance at the word line (5). (16c) is a third MoS transistor connected between one electrode of the first MOS transistor and a power line (8) serving as a predetermined potential point, and whose gate electrode is connected to the -PR line; (17a) and (17b) are capacitors. Also, Figure 7 shows the 5th
FIG. 3 is a circuit diagram of one word line in the figure. In the same figure, Oa is an X decoder disposed on the drive end side of the word line, 09 is a word driver disposed adjacent to this X decoder, and ■ is the first control shown in FIG. 8(a). The PR line through which the PR signal is sent is shown in Figure 8 (d).
fG times the second control signal shown in l.
The line and ■ indicate the word line (
5) drive end, ■ is the terminal end of the word line (5) that rises with the waveform shown in FIG. 8 (cl), and (b) is the opposing electrode of the memory capacitor that discharges with the rise waveform shown in FIG. 8 (e). The discharge end of , ■ is the end of the waveform shown in FIG. 8 (fl).

Next, the operation of the MOS dynamic memory with the above configuration will be explained with reference to FIG. First, when the word line (5) selected by the X decoder decoy is driven by the word driver (1! As shown in FIG. 8 (d), the word line (5)
The rising edge of ■ is delayed. At this time, due to the delayed rise of the word signal line shown in FIG. figure(
The discharge of the counter electrode 09 of the memory capacitor corresponding to the waveform shown in FIG. 8 (cl), which is the most delayed in the rise of the word line signal, is delayed as shown in FIG. It becomes faster as shown in el. Also, in Fig. 8 (f
Since the word line signal shown in FIG. 8 fbl corresponding to the counter electrode 05i of the memory capacitor whose discharge is delayed shown in l rises at a high speed, the signal charge is transferred from the memory cell u3 to the bit line (4) at a high speed. The word line signal delay is compensated for. On the other hand, the counter electrode (151) of the memory container is charged by setting the -GM signal to a high level after detecting and amplifying data by the sense amplifier circuit (2) and before connecting to the word line (5). As is clear from the circuit shown in FIG. 7, the opposing electrode 05! of the memory capacitor is charged and discharged only for the selected word line (5). The counter electrode QS is held at the power supply voltage VDD level by the precharge signal -PH during the precharge time.Therefore, the word line (5)
It can be seen that even if the level of VDD is the power supply voltage VDD, no loss of the threshold voltage of the transfer gate occurs.

Next, the operation of the memory cell (13) in the operation of one word line shown in FIGS. 7 and 8 (al to 8(fl) is described in FIGS. , 1st
1 and 12 (al^Fig. 12 (dl). First, Fig. 9 shows the memory cell near the word driver (
13 is shown, and the state of the surface potential development of the memory cell at time Tl-74 shown in FIGS. 8 (al to 8 (fl) is shown in FIGS.
Shown below. As can be seen from these figures, since the rise of the word line signal in the memory cell 03 near the word driver is warm, signal charges are transferred to the bit line (4) at high speed.

Moreover, FIG. 11 shows a cross-sectional view of the memory cell (131) farthest from the word driver, and FIG.
Figure 12 (al to 12th
As shown in the figure (dl), as can be seen from these figures, in the memory cell 03 farthest from the word driver, the opposite electrode of the memory capacitor is discharged at high speed before the word line signal rises sufficiently. It is also shown that the signal charges are transferred to the bit line (4) at high speed.It is also shown that there is no loss of the threshold voltage VT of the transfer gate in the signal charges that can be handled simultaneously.

As described in detail above, according to the MOS dynamic memory according to the present invention, a decoder for selectively driving the word line is provided at one end of the word line, and other word lines arranged in the corresponding column are provided with a decoder for selectively driving the word line. One electrode of the memory cell of the memory cell connected to the end and arranged in the corresponding column is discharged when the potential of the word line arranged in the corresponding column changes from a low level to a high level, and the word line Since a cell counter electrode control circuit that charges while the cell is selectively driven is provided in each column, word line delay due to RC components is compensated for, and a large signal voltage can be obtained at high speed. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a memory array of a conventional MOS dynamic memory, FIG. 2 is a detailed cross-sectional view of the memory cell in FIG. 1, and FIG. 3 is a configuration diagram showing a memory array of another conventional MOS dynamic memory. 4 is a detailed sectional view of the memory cell shown in FIG. 3, FIG. 5 is a configuration diagram showing an embodiment of the MOS dynamic memory according to the present invention, and FIG. 6 is the counter electrode control circuit shown in FIG. 5. Detailed circuit diagram of 7th
The figure is a circuit diagram for one word line in Figure 5, Figure 8 (a1 to Figure 8) is a diagram showing the waveforms of each part in Figure 7, and Figure 9 is a memory cell near the word driver. 10 (at to 10 (dl is a diagram showing the state of the surface potential of the memory cell in FIG. 9, FIG. 11 is a sectional diagram of the memory cell farthest from the word driver, and FIG. 12 is a cross-sectional view of the memory cell farthest from the word driver. (
at to FIG. 12Fdl are diagrams showing the state of the surface potential of the memory cell of FIG. 11. il+ 13...Memory cell, (4)...Bit line pair, (5)...Word line, α4)...Counter electrode control circuit, a9...Memory container counter electrode (one electrode ), (16a) to (16c)...MOS transistors, (181...X decoder, (11...word driver, (211...control signal). Note that the same lines The symbol indicates a portion or an equivalent portion.

Claims (2)

[Claims] (1) They are arranged in a matrix in multiple rows and columns, each consisting of one transfer gate and one memory capacitor, and the electrodes of one of the memory capacitors arranged in the corresponding column are electrically connected to each other. A plurality of connected memory cells, each arranged in each column, a plurality of word lines to which the memory cells arranged in the corresponding column are connected, each arranged in each row, and one arranged in the corresponding row. A plurality of bit lines to which memory cells are connected, a decoder disposed at one end of the word line for selectively driving the word line, and a word disposed in each column and arranged in the corresponding column. One electrode of the memory capacitor of the memory cell connected to the other end of the line and arranged in the corresponding column is discharged when the potential of the word line arranged in the corresponding column changes from a low level to a high level. ,
A MOS dynamic memory equipped with a plurality of cell counter electrode control circuits that charge while word lines are selectively driven. (2) In the cell counter electrode control circuit, the gate electrode is connected to the other end of the word line arranged in the corresponding column, and one electrode is connected to one electrode of the memory capacitor arranged in the corresponding column. and a MOS transistor to which a control signal is applied to the other electrode, which is set to a low level before the word line is selectively driven, and changes from a low level to a high level while being selectively driven. The MOS dynamic memory according to claim 1, characterized in that: