JPS5690A - Random access memory - Google Patents

Random access memory

Info

Publication number
JPS5690A
JPS5690A JP7586679A JP7586679A JPS5690A JP S5690 A JPS5690 A JP S5690A JP 7586679 A JP7586679 A JP 7586679A JP 7586679 A JP7586679 A JP 7586679A JP S5690 A JPS5690 A JP S5690A
Authority
JP
Japan
Prior art keywords
memory
word line
stored
difference
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7586679A
Other languages
Japanese (ja)
Inventor
Yoshiharu Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7586679A priority Critical patent/JPS5690A/en
Publication of JPS5690A publication Critical patent/JPS5690A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To constitute a memory of large strage capacity with sure storage, by making greater the difference of potentials when ''H'' is stored in the charge storage section of memory cell and when ''L'' is stored. CONSTITUTION:The memory 1 consisting of MOS transistor Q1, capacitor C1 and charge storage section 2, is provided with the word line 4a connected to the capacitor C1 and the word line 4 connected to the source of the MOS transistor Q1, and the part between them is connected with the inverter 4b and the sens amplifier 7 is provided, which is connected to the decoder 5 and the bit line 6. Accordingly, by giving double power supply voltage than at ''H'' to the word line 4a and giving zero voltage at ''L'', the difference between the stored charges due to level difference between ''H'' and ''L'' of charge sotrage section 2 is doubled, allowing to produce large strage capacity of memory through ease of detection and sure storage.
JP7586679A 1979-06-15 1979-06-15 Random access memory Pending JPS5690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7586679A JPS5690A (en) 1979-06-15 1979-06-15 Random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7586679A JPS5690A (en) 1979-06-15 1979-06-15 Random access memory

Publications (1)

Publication Number Publication Date
JPS5690A true JPS5690A (en) 1981-01-06

Family

ID=13588595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7586679A Pending JPS5690A (en) 1979-06-15 1979-06-15 Random access memory

Country Status (1)

Country Link
JP (1) JPS5690A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5832296A (en) * 1981-08-20 1983-02-25 Mitsubishi Electric Corp Mos dynamic memory
JPH03192594A (en) * 1990-10-22 1991-08-22 Mitsubishi Electric Corp Mos dynamic memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5832296A (en) * 1981-08-20 1983-02-25 Mitsubishi Electric Corp Mos dynamic memory
JPH03192594A (en) * 1990-10-22 1991-08-22 Mitsubishi Electric Corp Mos dynamic memory

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