JPH0319281A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory cell having a large capacity of the cell and a large operation margin by efficiently utilizing the periphery of a cell plate electrode as the capacity of the cell. CONSTITUTION:In a memory cell having a source 4 as a charge storage node, a cell plate electrode 9 is provided on a gate insulating film 5 on a source. An opening 13 is opened at the electrode 9, a second gate insulating film 8 is provided at the periphery of the opening and at the top of the electrode 9, a charge storage polysilicon electrode 7 is attached on the film 9, and the source 4 is connected to it through the opening 13. It is covered with an interlayer insulating film 11, an opening 12 is opened, and Al wiring 10 is formed and connected to a drain 3. Since the upper and side faces of the electrode 9, the periphery of the opening of the electrode 9 and the lower face of the electrode 9 are used as capacities, the capacity of the cell can be increased, and the memory cell having a large operation margin is obtained.

Description

[Detailed description of the invention] Industrial applications The present invention relates to memory.

2. Description of the Related Art In recent years, semiconductor memory devices have become more densely packed, especially DRA.
The highly integrated, high-density body is impressive. The development of DRAM is largely due to the development of high-density technology for memory cells, which occupy more than half of the chip size. FIG. 2 shows an example of such a memory cell.

In the figure, 1 is a silicon substrate, 2 is an element isolation region, 3 is a drain forming a bit line, 4 is a source forming a charge storage node, 5 is a gate insulating film of a MOB transistor for signal readout, and 6 is a word line. For example, a gate electrode made of polysilicon, 7 a polysilicon electrode for charge storage, 8 a capacitor insulating film for charge storage, 9 a cell plate electrode made of polysilicon, and 1o made of aluminum, for example, forming a bit line. The formed wiring, 11 is an insulating film between the eyebrows, 12 is a contact window for connecting the bit line 10 to the drain 3, and 13 is a contact window for connecting the charge storage electrode 7 to the source 4. . This is a so-called stacked memory cell μ (stacked memory cell lv).

This memory cell μ stores information on the bit line 1o from the drain 3 to the source 4, and stores it in a certain memory cell capacitor from 7, 8.9 so that the word electrode 6 is set to logic voltage “H”. (write operation) or read out the written information in the memory capacitor to the 10th bit line (read operation).

This memory cell can have a larger capacitor area than the conventional planar type 7P, and does not require sophisticated process technology unlike the trench type 7P.

Problems to be Solved by the Invention However, in the conventional example described above, although the planar type capacitor can obtain a large capacitor area, it is difficult to operate because the capacitor is formed only with the upper and side surfaces of the polysilicon electrode for charge storage. It has been difficult to obtain sufficient cell capacity to ensure margins.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a semiconductor memory cell in which the surface layer capacitor area is large.

Means for Solving the Problems In order to achieve this object, the memory device of the present invention has a cell plate electrode sandwiching the source of the read MOS transistor and the first gate oxide film, and A charge storage electrode is provided around an opening provided in the plate electrode and across a second gate oxide film formed on the cell plate electrode, and the charge storage electrode is provided in the cell plate. It has a configuration in which it contacts the source through an opening.

According to the memory device of the present invention, not only the top and side surfaces of the cell plate electrode, but also the periphery of the opening provided in the cell plate electrode and the bottom surface of the cell plate electrode are utilized as a capacitor portion. Therefore, it is possible to obtain a memory cell with a large operating margin, which allows the cell capacitance to be increased.

Embodiments Hereinafter, embodiments of the memory cell of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing one embodiment of the present invention. All symbols in the figure are the same as in the description of the conventional example. As you can see from the figure, the cell plate voltage is 1! i9 is also placed below the charge storage polysilicon electrode 7, and the charge storage polysilicon electrode 7 is placed below the cell plate voltage fM.
Since it is not in contact with the source 4 through the opening provided in the cell plate electrode 9, the area around the cell plate electrode 9 can be effectively used as a capacitor.

Effects of the Invention As described above, if the memory 7μ of the present invention is used, the area around the 7P plate electrode can be efficiently used as a cell capacitor, so a memory cell with a large cell capacity and a large operating margin can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining one embodiment of the memory 7 of the present invention, and FIG. 2 is a sectional view for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Element isolation region, 3... Drain constituting a bit line, 4
... Source configuring the charge storage node, 5...
...Gate oxide film of MOS transistor, 6...
...MOS} transistor gate electrode, 7...
・Polysilicon electrode for charge storage, 8...Capacitor insulating film for charge storage, 9...Cell plate electrode using polysilicon, 10...Constitutes a bit line Aluminum wiring, 11...Interlayer insulating film, 1
2...Contact window for connecting the bit line to the drain, 13...Contact window for connecting the charge storage electrode to the drain.

Claims (1)

[Claims] In a semiconductor memory cell in which a drain side of a MOS transistor formed on a semiconductor substrate having one conductivity type constitutes a bit line and a source side constitutes a charge storage node, a first gate insulating film is provided on the source. A conductive electrode forming a cell plate electrode is provided on the first gate insulating film, and a second gate insulating film is provided around the opening provided in the cell plate electrode and above the cell plate electrode. a conductive electrode constituting a charge storage electrode on the second gate insulating film, and the charge storage electrode is connected to the source through an opening provided in the cell plate electrode. A semiconductor memory cell characterized by being in contact with each other.