JPH03230564A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a small memory cell and a small-sized chip by forming a part of a memory cell transistor and a memory cell capacitor inside a trench. CONSTITUTION:A semiconductor memory device comprises a contact window 12 which connects a bit line 1 to a drain part 2, a contact window 13 which connects a source part 9 to a charge storage part 10 and a trench part 14 formed inside a substrate 8. A gate electrode 3 and the charge storage part 10 of a memory cell are formed inside the trench part 14 so that a memory cell transistor and a memory cell capacitor can be formed with a small area. Thus an area of the memory cell can be reduced without reducing a gate length and a gate width of the transistor and without reducing memory cell capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device.Recently, the density of semiconductor memory devices has been increasing, and in particular, dynamic random access memory (DRAM) has become more dense. The increase in integration and density is remarkable. This development of RAM is largely due to the memory cell structure, which occupies more than half of the chip size. Figure 2 shows
This is an example of such a memory cell. FIG. 2(A) is a plan view of a main part of a memory cell, and FIG. 2(B) is a sectional view taken along line aa' in FIG. 2(A). 1 is a conductor constituting the bit line, 2
Same L: <Drain part connected to the bit line, 3 is the gate electrode of the signal readout MOs transistor forming the word line, 4 is the gate insulating film of the signal readout MOs transistor, 5 is the cell plate voltage source 6 is an insulating film for cell isolation, 7 is an interlayer insulating film between each conductor, 8 is a substrate of the opposite conductivity type to 2,
9 is the source part of the memory cell, 10 is the voltage ig of the memory cell.
The product s, 11 is an insulating film constituting the memory cell capacitor,
12 is a contact window that connects the bit line 1 and the drain section 2; and 13 is a contact window that connects the source section 9 and the charge storage section 10. This is a so-called stacked memory cell. In this memory cell, by setting the gate electrode constituting the word line 3 to logic voltage "H", information on the bit line 1 is transmitted from the drain section 2 through the source section 9 to the memory cell 10. An operation is performed in which information is stored in the charge storage section (write state) or information stored in the charge storage section of 10 memory cells is read out to one bit line (read state).

Problems to be Solved by the Invention In the conventional memory cell described above, memory cell transistors are formed only on two sides of the semiconductor substrate.
When trying to reduce the memory cell area in order to increase the degree of integration, the gate length and gate width of the transistor become smaller, and as the gate length becomes shorter, charge leaks between the source and drain parts of the transistor, which causes the memory cell capacitor to become smaller. The charge in the charge storage section is easily destroyed, and if the gate width becomes narrow, the threshold voltage of memory cell 1 to the transistor increases, which slows down the readout of charge from the charge storage section of the memory cell capacitor, leading to malfunction. There was a problem.

Means for Solving the Problems A semiconductor memory device of the present invention includes a trench formed in a semiconductor substrate of a conductivity type, and a source portion of a conductivity type opposite to that of the semiconductor substrate formed in at least a portion of the bottom of the trench. , a gate insulating film including at least a peripheral portion of the surface of the source portion and formed on at least an inner wall of the trench, a gate electrode formed inside the trench, an interlayer insulating film formed on the gate electrode, A charge storage section formed on an interlayer insulating film, an insulating film formed on the charge storage section, and a cell plate electrode formed on the insulating film, the charge storage section being connected to the source section. has been done.

As described above, in the memory cell of the present invention, a part of the memory cell transistor and the memory cell capacitor are formed inside the trench, so that the memory cell capacitance can be reduced without reducing the gate length and gate width of the transistor. It is possible to reduce the area without reducing the size.

EXAMPLE Hereinafter, the present invention will be explained by way of an example with reference to FIG. FIG. 1 is a diagram showing an embodiment of the present invention, in which (A) is a plan view of essential parts of a memory cell, and (B) is a-a in (,A).
FIG. 1 is a conductor that constitutes a bit line, 2 is a drain part also connected to the focus line, 3 is a gate electrode of a MO transistor for signal readout that constitutes a word line, and 4 is a gate insulation of the MOS transistor for signal readout. 5 is a self-rate electrode connected to a cell plate voltage source, 6 is an insulating film for cell isolation, 7 is an interlayer insulating film between each conductor, 8 is a substrate of the opposite conductivity type to the drain part 2, and 9 is a Memory cell source section, 10 Hammemo'7
The charge storage part of the cell, 11 is an insulating film constituting the memory cell, 12 is a contact window connecting the 11 and the drain part 2, and 13 is the source part 9 and the charge storage part 10.
A contact window 14 is a trench portion formed in the substrate 8. The gate electrode 3 and the charge storage section 10 of the memory cell are formed within the trench section 14, so that a memory cell transistor and a memory cell capacitor can be formed in a small area. Comparing a conventional memory cell created according to the same layout rule and a memory cell embodiment of the present invention, the memory cell area is 7.92 μm in the conventional example and 5.76 μm in the present invention, which forms a memory cell capacitor. The area of the portion is 3.11μ in the conventional example, 1°81μ in the present invention, and 2° in the trench depth.
．． If it is 5 μm, it will be 2.82 μm and the total will be 4.6
It is 3 μM. From this, when calculating the memory cell capacity, we get SiO2·ε in the memory cell capacity Cs-. /10, relative permittivity of oxide film 5iO2 = 3.9 relative permittivity in vacuum εo
= 8.86 x 10 ''coulombs/'h cm Insulating oxide film thickness t of memory cell capantor. = 8 nm From this, the memory cell capacity of the conventional memory cell is 13.4 fF, and the memory cell capacity of the memory cell of the present invention is 20 .0 f F. In this way, the memory cell area was reduced to 72.7%, the memory cell capacity increased to 154%, and we were able to secure 20.OfF. Regarding the operation, it is the same as the conventional one. By setting the gate electrode constituting the word line 3 to logic voltage "H", information on the bit line 1 is stored from the drain section 2 through the source section 9 to the charge storage section 10 of the memory cell ( Writing state B) or reading out the information stored in the charge storage section 10 of the memory cell onto the bit line 1 (reading state) is performed.

Effects of the Invention As described above, according to the semiconductor memory device of the present invention, a very small memory cell and a chip with a small area can be provided, and an inexpensive semiconductor memory device can be provided. The practical effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, in which FIG. 1(A) is a plan view of a main part, and FIG. 1(B) is a line taken along line a-a' in FIG. 1(A). 2 is a diagram showing a conventional semiconductor memory device, FIG. 2(A) is a plan view of a main part, and FIG. 2(B) is a cross-sectional view taken along a-a' of FIG. 2(A). It is a sectional view along the line. 1... Conductor forming the bit line, 2...
...Drain part connected to the bit line, 3...
Gate electrode constituting a word line, 4...gate insulating film, 5...cell plate electrode, 6...
... Insulating film for cell separation, 7... Interlayer insulating film,
8... Substrate, 9... Source part of memory cell, 1o... Charge storage part of memory cell, 11...
...Insulating film constituting a memory cell capacitor, 1
2... Contact window connecting the bit line and the drain part, 13... Source part 9 and charge storage part 10
contact window, 14...trench portion formed in the substrate.

Claims (1)

[Claims] A trench formed in a semiconductor substrate of one conductivity type and a semiconductor substrate formed in at least a portion of the bottom of the trench include a source part of an opposite conductivity type and at least a peripheral part of the surface of the source part, and at least the trench a gate insulating film formed on an inner wall, a gate electrode formed inside the trench, an interlayer insulating film formed on the gate electrode, and a charge storage section formed on the interlayer insulating film;
A semiconductor memory device comprising an insulating film formed on the charge storage section and a cell plate electrode formed on the insulating film, the charge storage section being connected to the source section.