JPH0319344A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0319344A
JPH0319344A JP1155065A JP15506589A JPH0319344A JP H0319344 A JPH0319344 A JP H0319344A JP 1155065 A JP1155065 A JP 1155065A JP 15506589 A JP15506589 A JP 15506589A JP H0319344 A JPH0319344 A JP H0319344A
Authority
JP
Japan
Prior art keywords
film
resist
barrier metal
resists
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1155065A
Other languages
Japanese (ja)
Inventor
Yoshimi Shirakawa
良美 白川
Hitoshi Hasegawa
長谷川 斉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1155065A priority Critical patent/JPH0319344A/en
Publication of JPH0319344A publication Critical patent/JPH0319344A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the yield and quality of a semiconductor device having a gold bump by a method wherein a plurality of resists, which respectively consist of a low first resist, which has a good accuracy of patterning and is easy to remove, and an upper second resist having a good plating resistance, are applied and patterned, a bump electrode is formed using these resists as masks, a plurality of the resists are removed and a barrier metal film is etched away. CONSTITUTION:A barrier metal film 4 is applied on a PSG film 3 including an opening part 6. Then, a ZPR first resist 11 is applied on the upper surface of the film 4 and moreover, an OFPR second resist 12 is formed. Here, the ZPR first resist 11 can be patterned with high precision, is easily removed and the OFPR second resist 12 is superior in a plating resistance. Then, a resist film mask 10, which has an opening part slightly wider than the opening part 6 and consists of the first and second resists 11 and 12, is formed at the position of the opening part 6. Then, a gold bump 15 is formed by plating in the opening part using the mask 10 as a protective film and using the film 4 as a plated electrode. Then, the mask 10 is dissolved and removed and the exposed film 4 is etched away.

Description

【発明の詳細な説明】 〔概要] 金属バンプの形成方法に関し、 歩留,品質を高めることを目的とし、 平坦電極を設けた半導体基板上に絶縁膜を被着L7、該
絶縁膜をパターンニングして前記平坦電極部分を開口す
る工程、次いで、前記平坦電極部分および絶縁膜上の全
面にバリヤ金属膜を被着する工程、 次いで、複数のレジスト(例えば、バクーンニング積度
が良くて除去され易い下層の第1レジストと、耐メノキ
性の良い上層の第2レジストとからなるレジスト)を被
着し、前記平坦電極部分を開ロして前記バリヤ金属膜を
露出させ、且つ、他部分をヤスクした前記複数のレジス
トからなるレジスト膜マスクを形成する工程、 次いで、前記バリヤ金属膜を電極にして、前記開口部の
前記ハリヤ金属膜上に金属バンプをメッキ形成する工程
、次いで、前記複数のレジスト膜を除去し、前記金属バ
ンプをマスクにして露出した前記バリヤ金属膜をエッチ
ング除去する工程が含まれることを特徴とする。
[Detailed Description of the Invention] [Summary] Regarding the method of forming metal bumps, for the purpose of improving yield and quality, an insulating film is deposited on a semiconductor substrate provided with a flat electrode L7, and the insulating film is patterned. Then, a step of depositing a barrier metal film on the entire surface of the flat electrode portion and the insulating film, and then a step of depositing a plurality of resists (for example, a resist film with a good Bakooning thickness and being removed). A resist consisting of a first resist (lower layer that is easy to resist) and a second resist (an upper layer that has good acetic acid resistance) is deposited, the flat electrode portion is opened to expose the barrier metal film, and the other portions are exposed. a step of forming a resist film mask made of the plurality of masked resists, a step of plating a metal bump on the barrier metal film in the opening using the barrier metal film as an electrode, and a step of plating the plurality of The method is characterized in that it includes a step of removing the resist film and etching away the exposed barrier metal film using the metal bump as a mask.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法のうち、特に金属バンプ
の形戒方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming metal bumps.

金属パンプ(bump)を設けた半導体装置は、ワイヤ
ーをボンディングする必要がないために、半導体容器の
厚みを薄くでき、且つ、半導体チップのボンディングパ
ッド(電極領域)も小さくできて、半導体容器を偏平な
形状にしてICカードに組み込んだり、また、多ピンI
Cを高集積化できる利点を有する構造である。更に、複
数の半導体チップを回路基板に配置して複合デバイスに
作或できるため、電子回路を高密度実装できる利点があ
る。
Semiconductor devices equipped with metal bumps do not require wire bonding, so the thickness of the semiconductor container can be made thinner, and the bonding pads (electrode areas) of the semiconductor chip can also be made smaller, making it possible to flatten the semiconductor container. It can be built into an IC card in a different shape, or it can be used as a multi-pin IC.
This structure has the advantage that C can be highly integrated. Furthermore, since a plurality of semiconductor chips can be arranged on a circuit board to create a composite device, there is an advantage that electronic circuits can be mounted in high density.

このような金属バンプを設けた半導体装置は、最近、そ
の高密度化の利点から再び見直されて再検討されつつあ
る。
Semiconductor devices provided with such metal bumps have recently been reconsidered and reconsidered due to their advantages in increasing density.

〔従来の技術〕[Conventional technology]

第2図は金属バンプ電極の断面図を示しており、1は半
導体基板,2はアルミニウムからなる平坦電極(アルミ
ニウム電極),3は燐シリケートガラス(P S G)
膜からなる絶縁膜,4はTi (チタン〉とPd (パ
ラジウム)の複合膜からなるバリヤ金属膜,5は金(A
u)からなるマッシュルーム型の金属バンプ(金バンプ
)である。
Figure 2 shows a cross-sectional view of a metal bump electrode, where 1 is a semiconductor substrate, 2 is a flat electrode made of aluminum (aluminum electrode), and 3 is phosphorus silicate glass (PSG).
4 is a barrier metal film made of a composite film of Ti (titanium) and Pd (palladium), and 5 is gold (A).
It is a mushroom-shaped metal bump (gold bump) consisting of u).

このような金属バンプの従来の形成方法の工程順断面図
を第3図(a)〜(『)に示している。その概要を説明
すると、 第3図(al参照;まず、半導体基板1上に設けたアル
ミニウム電極2を含む基板全面に、化学気相威長(CV
D)法によってPSG膜3(カバー絶縁膜)を成長する
。なお、PSG膜3の代わりに、酸化シリコン(SiO
z)膜を用いる場合もある。
Step-by-step sectional views of the conventional method for forming such metal bumps are shown in FIGS. 3(a) to 3('). To explain the outline of the process, as shown in FIG. 3 (see al; first, chemical vapor deposition (CV
D) A PSG film 3 (cover insulating film) is grown by method. Note that instead of the PSG film 3, silicon oxide (SiO
z) A membrane may be used in some cases.

第3図(bl参照;次いで、フォトプロセスを適用して
PSG膜3をエソチングして、アルミニウム電極2上に
開口部6を形成する。
FIG. 3 (see BL; see FIG. 3; next, the PSG film 3 is etched using a photo process to form an opening 6 on the aluminum electrode 2.

第3図(Cl参照;次いで、マスクを除去した後、開口
部6を含むPSG膜3上にバリヤ金属膜4を蒸着法で被
着する。
FIG. 3 (see Cl; then, after removing the mask, a barrier metal film 4 is deposited on the PSG film 3 including the opening 6 by vapor deposition.

第3図(d)参照;次いで、レジスト膜を塗布し、露光
・現像して前記開口部6の位置に開口部よりやや広い開
口部7を有するレジスト膜マスク8を形成する。
Refer to FIG. 3(d); next, a resist film is applied, exposed and developed to form a resist film mask 8 having an opening 7 slightly wider than the opening 6 at the position of the opening 6.

第3図tel参照;次いで、レジスト膜マスク8を被覆
した状態で、バリヤ金属膜4をメッキ電極として開口部
7に金バンプ5を鍍金法でメッキする。
Refer to FIG. 3 (tel); Next, with the resist film mask 8 covered, gold bumps 5 are plated in the openings 7 using the barrier metal film 4 as a plating electrode by a plating method.

この時、レジスト膜マスク8で被覆された部分はメッキ
されない。
At this time, the portion covered with the resist film mask 8 is not plated.

第3図(f)参照;次いで、レジスト膜マスク8を除去
し、更に、露出したバリヤ金属膜4をエッチング除去す
る。このようにして、アルξニウム電極2の上にバリヤ
金属膜4を介した金ハンブ5が形成される。
Refer to FIG. 3(f); next, the resist film mask 8 is removed, and the exposed barrier metal film 4 is further etched away. In this way, the gold humb 5 is formed on the aluminum ξ electrode 2 with the barrier metal film 4 interposed therebetween.

上記が従来の金属バンプの形成方法の概要である。The above is an overview of the conventional method for forming metal bumps.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、このような金属バンプ電極の形戒方法は、レ
ジスト膜マスク8を被覆してマノシュルーム型の金バン
ープを形成し、次いで、レジスト膜マスク8を除去し、
更に、バリヤ金属膜4をエッチング除去する方法である
から、レジスト膜マスク8に関わりのある不具合が起こ
る。即ち、レジスト膜マスク8を被覆膜として厚い(高
さ50μm程度)金バンプをメッキ形成する鍍金工程で
は、レジスト膜の剥がれが生じて、不必要な部分にメッ
キ層が被着して、そのメッキ異常のために不良品ができ
る。
However, in this method of forming metal bump electrodes, a manoshroom-type gold bump is formed by covering the resist film mask 8, and then the resist film mask 8 is removed.
Furthermore, since the method involves removing the barrier metal film 4 by etching, problems related to the resist film mask 8 occur. That is, in the plating process in which thick (approximately 50 μm in height) gold bumps are plated using the resist film mask 8 as a covering film, the resist film peels off, and the plating layer adheres to unnecessary areas. Defective products are produced due to plating abnormalities.

また、マッシュルーム型に金バンプをメソキするために
、レジスト膜マスク8やバリヤ金属膜4をエソチング除
去しても完全に除去されず、マ・7シュルームの傘下に
それらの残渣が残こり、素子特性に悪影響を与えること
が起こる。
In addition, even if the resist film mask 8 and the barrier metal film 4 are removed by etching to form the mushroom-shaped gold bumps, they are not completely removed, and their residue remains under the mushroom-shaped mushroom, which may affect the device characteristics. may have a negative impact on.

特に、口径6インチφ程度の大口径化ウエハーでは、全
面に均一な膜厚のレジスト膜マスク8を一様に形成する
ことが困難で、ウエハー面にレジスト膜厚の不均一が生
じ、且つ、レジストを厚く塗布するほど、ウエハー全面
での膜厚の不均一性が激しくなり、これが上記の問題を
倍加させている。
In particular, in the case of large-diameter wafers with a diameter of about 6 inches φ, it is difficult to uniformly form the resist film mask 8 with a uniform film thickness over the entire surface, and the resist film thickness becomes non-uniform on the wafer surface. The thicker the resist is coated, the greater the non-uniformity of the film thickness across the wafer, which doubles the above problem.

本発明はこれらの問題点を解消させ、金属バンプを有す
る半導体装置の歩留,品質を高めるための製造方法を提
案するものである。
The present invention proposes a manufacturing method for solving these problems and improving the yield and quality of semiconductor devices having metal bumps.

次いで、複数のレジスト (例えば、パターンニング精
度が良くて除去され易い下層の第1レジストと耐メソキ
性の良い上層の第2レジストからなる複数のレジスト)
を被着し、前記平坦電極部分を開口して前記バリヤ金属
膜を露出させ、且つ、他部分をマスクした前記複数のレ
ジストからなるレジスト膜マスクを形成する工程、 次いで、前記バリヤ金属膜を電極にして、前記開口部の
前記バリヤ金属膜上に金属バンプをメッキ形成する工程
、次いで、前記複数のレジスト膜を除去し、前記金属バ
ンプをマスクにして露出した前記バリヤ金属膜をエッチ
ング除去する工程が含まれる製造方法によって解決され
る。
Next, a plurality of resists (for example, a plurality of resists consisting of a lower layer first resist that has good patterning accuracy and is easy to remove, and an upper layer second resist that has good mesoki resistance)
forming a resist film mask consisting of the plurality of resists, opening the flat electrode portion to expose the barrier metal film, and masking other portions; plating a metal bump on the barrier metal film in the opening, then removing the plurality of resist films, and etching away the exposed barrier metal film using the metal bump as a mask. is solved by a manufacturing method that includes

[課題を解決するための千段] その課題は、平坦電極を設けた半導体基板上に絶縁膜を
被着し、該絶縁膜をパターンニングして前記平坦電極部
分を開口する工程、次いで、前記平坦電極部分および絶
縁膜上の全面にバリヤ金属膜を被着する工程、 [作用] 即ち、本発明では複数のレジストを被着する多層塗りを
おこない、例えば、パターンニング精度が良くて除去さ
れ易い下層の第1レジストと耐メッキ性の良い上層の第
2レジストからなる複数のレジストを被着してパターン
ニングし、これをマスクにしてバンプ電極を形威し、そ
して、その複数のレジストを除去し、更に、バリヤ金属
膜をエソチング除去する。
[A Thousand Steps to Solve the Problem] The problem is a step of depositing an insulating film on a semiconductor substrate provided with a flat electrode, patterning the insulating film to open the flat electrode portion, The step of depositing a barrier metal film on the flat electrode portion and the entire surface of the insulating film [Function] In other words, in the present invention, multi-layer coating is performed in which a plurality of resists are deposited. For example, the barrier metal film has good patterning accuracy and is easy to remove. A plurality of resists consisting of a first resist as a lower layer and a second resist as an upper layer with good plating resistance is deposited and patterned, this is used as a mask to form a bump electrode, and then the plurality of resists are removed. Then, the barrier metal film is removed by etching.

このようにレジストの多層塗りすれば、厚いレジストを
ウエハー全面に均一な膜厚で被覆することができ、その
ため、ウエハー全面の素子に均一なバンプ電極が形成さ
れ、マソシュルーム下の残渣も減少して、半導体装置の
歩留,品質を向上させることができる。
By applying multiple layers of resist in this way, it is possible to coat the entire wafer with a thick resist with a uniform thickness, and as a result, uniform bump electrodes are formed on the elements over the entire wafer, and the residue under the massoshroom is also reduced. , the yield and quality of semiconductor devices can be improved.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(a)〜(e)は本発明にかかる形成方法の工程
順断面図を示しており、順を追って説明すると、第1図
(al参照;まず、半導体基板1上に設けたアルミニウ
ム電極2 (膜厚lμm前後)を含む基板全面にPSG
膜3 (膜厚1μm程度)を戒長し、そのPSG膜3を
エソチングしてアルミニウム電極2上に開口部6を設け
、その開口部6を含むPSG膜3上にバリヤ金属膜4を
被着する。なお、バリヤ金属膜4は蒸着法で被着したT
i膜(膜厚3000人)とPd膜(膜厚2000人)と
の2層からなる膜である。また、アル【ニウム電極2の
面積は約100μm角の大きさである。
FIGS. 1(a) to 1(e) show step-by-step cross-sectional views of the forming method according to the present invention. PSG is applied to the entire surface of the substrate including electrode 2 (film thickness around 1 μm).
A film 3 (film thickness of about 1 μm) is lengthened, the PSG film 3 is ethoched to form an opening 6 on the aluminum electrode 2, and a barrier metal film 4 is deposited on the PSG film 3 including the opening 6. do. Note that the barrier metal film 4 is a T film deposited by a vapor deposition method.
The film consists of two layers: an i film (thickness: 3,000 yen) and a Pd film (thickness: 2,000 yen). Further, the area of the aluminum electrode 2 is approximately 100 μm square.

第1図(bl参照;次いで、その上面にZPR (ゼオ
ンポジレジスト)からなる第1レジス1・1)を塗布し
キュアさせて、3μm前後の膜厚にした後、更に、○F
PR (東京応化ボジレジスト)からなる第2レジスト
12を塗布しキュアさせて、同じく3μm前後の膜厚に
形成する。ここに、ZPRはヒビ割れが起き易いが、パ
ターンニングして高精度にパターンニングできて、且つ
、爾後に除去の容易なことが特色のレジストであり、又
、OFPRは耐メッキ性に優れたことを特色とするレジ
ストである。
Figure 1 (see BL; Next, first resist 1.1) made of ZPR (Zeon Positive Resist) was applied to the top surface and cured to a film thickness of around 3 μm.
A second resist 12 made of PR (Tokyo Ohka Body Resist) is applied and cured to form a film having a thickness of approximately 3 μm. Although ZPR is prone to cracking, it is a resist that can be patterned with high precision and is easy to remove afterwards, and OFPR has excellent plating resistance. This resist is characterized by:

第l図(C)参照:次いで、露光・現像して前記開口部
6の位置に開口部よりやや広い開口部13を有する第1
レジスト1)および第2レジスト12からなるレジスト
膜マスク10を形成する。
Refer to FIG. 1(C): Next, a first film having an opening 13 slightly wider than the opening 6 at the position of the opening 6 is exposed and developed.
A resist film mask 10 consisting of a resist 1) and a second resist 12 is formed.

第1図(d)参照;次いで、レジスト膜マスク10を保
護膜とし、バリヤ金属膜4をメンキ電極として開口部I
3に金バンプ15 (直径100〜200μmφ,高さ
50μm程度)を鍍金法でメ・ノキ形戒する。その時、
レジスト膜マスク10で被覆された部分はメッキされな
い。
Refer to FIG. 1(d); Next, the resist film mask 10 is used as a protective film, and the barrier metal film 4 is used as a blanking electrode to open the opening I.
3, gold bumps 15 (diameter 100 to 200 μmφ, height approximately 50 μm) are formed into a metal wood shape using a plating method. At that time,
The portion covered with the resist film mask 10 is not plated.

第1図(e)参照:次いで、第1レジスト1)および第
2レジストl2からなるレジスト膜マスク10を溶解し
て除去し、更に、露出したバリヤ金属膜3をエッチング
除去する。このようにして、アルミニウム電極2の上に
バリヤ金属膜4を介した金バンプl5を形成する。
Refer to FIG. 1(e): Next, the resist film mask 10 consisting of the first resist 1) and the second resist 12 is dissolved and removed, and the exposed barrier metal film 3 is removed by etching. In this way, gold bumps 15 are formed on the aluminum electrode 2 with the barrier metal film 4 interposed therebetween.

上記のような形成方法を採れば、第2レジスト12は耐
メッキ性に優れているから鍍金工程でのレジスト膜の剥
がれが城少しで不良品が低減され、製造の歩留が向上す
る。また、多層塗りのためにレジスト膜マスク10の膜
厚を厚くできて、しかも、膜厚が均一になり、且つ、第
1レジスト1)はパターンニング残りが少ないレジスト
であるから、マンシュルーム型金バンプ下の残渣がなく
なって、高品質化ささる。更に、レジストは多層塗りで
あるから、大口径化したウエハー全面に均一な膜厚のレ
ジスト膜マスク10を一様に形成することができて、そ
の点から特に歩留,品質の向上に役立つ。
If the above-described formation method is adopted, the second resist 12 has excellent plating resistance, so the resist film is less likely to peel off during the plating process, reducing the number of defective products and improving the manufacturing yield. Furthermore, the thickness of the resist film mask 10 can be made thicker for multi-layer coating, and the film thickness can be made uniform, and since the first resist 1) is a resist with little patterning residue, it is possible to make the resist film mask 10 thicker. There is no residue under the bumps, resulting in higher quality. Furthermore, since the resist is applied in multiple layers, it is possible to uniformly form the resist film mask 10 with a uniform thickness over the entire surface of a large-diameter wafer, which is particularly useful for improving yield and quality.

且つ、上記実施例は金属バンプを金バンプとし、バリヤ
金属膜にTi膜とPd膜との2層膜を用いた製造方法で
説明したが、その他の部材、例えば、バリヤ金属膜にT
iW−八Uの2層金属膜,Cr−Cuの2層金属膜など
を用いても良く、また、半田バンプを形成する半導体装
置Cこも通用できることは云うまでもない。
In addition, although the above embodiment has been described using a manufacturing method in which the metal bumps are gold bumps and the barrier metal film is a two-layer film of a Ti film and a Pd film, other members, for example, T can be used in the barrier metal film.
It goes without saying that a two-layer metal film of iW-8U, a two-layer metal film of Cr-Cu, etc. can be used, and a semiconductor device C in which solder bumps are formed can also be used.

[発明の効果] 以上の説明から明らかなように、本発明によれば金属バ
ンプ電極を有する半導体装置において、金属バンプを形
成する際に不良品の発生を減少させ、且つ、ハンプ電極
下の残渣をなくして、その歩留,品質を向上させる大き
な効果が得られるものである。
[Effects of the Invention] As is clear from the above description, according to the present invention, in a semiconductor device having a metal bump electrode, the occurrence of defective products can be reduced when metal bumps are formed, and the residue under the hump electrode can be reduced. This has the great effect of improving yield and quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(elは本発明にかかる形成方法の工程
順断面図、 第2図は金属バンプ電極の断面図、 第3図ta+〜ff)は従来の形成方法の工程順断面図
である。 図において、 1は半導体基板、 2はアルミニウム電極(平坦電極)、 3はPSG膜(絶縁膜)、 4はバリヤ金属膜、 5,15は金ハンプ、 6,7.13は開口部、 8.10はレジスト膜マスク、 1)は第1レジスト、 12は第2レジスト を示している。 全属ハ・>7・4どる会Otケ盾l詔 第2図 一243
Figures 1 (al to el are step-by-step cross-sectional views of the forming method according to the present invention, Figure 2 is a cross-sectional view of a metal bump electrode, and Figure 3 ta+ to ff) are step-by-step cross-sectional views of a conventional forming method. In the figure, 1 is a semiconductor substrate, 2 is an aluminum electrode (flat electrode), 3 is a PSG film (insulating film), 4 is a barrier metal film, 5, 15 are gold humps, 6, 7, 13 are openings, 8.10 is a resist film mask, 1) is a first resist, and 12 is a second resist. All Genus Ha・>7・4 Dorukai Otke Shield I Edict No. 2 Figure 1 243

Claims (2)

【特許請求の範囲】[Claims] (1)平坦電極を設けた半導体基板上に絶縁膜を被着し
、該絶縁膜をパターンニングして前記平坦電極部分を開
口する工程、 次いで、前記平坦電極部分および絶縁膜上の全面にバリ
ヤ金属膜を被着する工程、 次いで、複数のレジストを被着し、前記平坦電極部分を
開口して前記バリヤ金属膜を露出させ、且つ、他部分を
マスクした前記複数のレジストからなるレジスト膜マス
クを形成する工程、 次いで、前記バリヤ金属膜を電極にして、前記開口部の
前記バリヤ金属膜上に金属バンプをメッキ形成する工程
、 次いで、前記複数のレジスト膜を除去し、前記金属バン
プをマスクにして露出した前記バリヤ金属膜をエッチン
グ除去する工程が含まれてなることを特徴とする半導体
装置の製造方法。
(1) A step of depositing an insulating film on a semiconductor substrate provided with a flat electrode, and patterning the insulating film to open the flat electrode portion. Next, a barrier is formed on the flat electrode portion and the entire surface of the insulating film. a step of depositing a metal film, then depositing a plurality of resists, opening the flat electrode portion to expose the barrier metal film, and forming a resist film mask made of the plurality of resists with other portions masked; Next, using the barrier metal film as an electrode, plating a metal bump on the barrier metal film in the opening; Next, removing the plurality of resist films and masking the metal bump. A method for manufacturing a semiconductor device, comprising the step of etching away the exposed barrier metal film.
(2)前記複数のレジストはパターンニング精度が良く
て除去され易い下層の第1レジストと、耐メッキ性の良
い上層の第2レジストとからなることを特徴とする請求
項(1)記載の半導体装置の製造方法。
(2) The semiconductor according to claim 1, wherein the plurality of resists includes a first resist as a lower layer that has good patterning accuracy and is easy to remove, and a second resist as an upper layer that has good plating resistance. Method of manufacturing the device.
JP1155065A 1989-06-16 1989-06-16 Manufacture of semiconductor device Pending JPH0319344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1155065A JPH0319344A (en) 1989-06-16 1989-06-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1155065A JPH0319344A (en) 1989-06-16 1989-06-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0319344A true JPH0319344A (en) 1991-01-28

Family

ID=15597902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1155065A Pending JPH0319344A (en) 1989-06-16 1989-06-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0319344A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649507B1 (en) * 2001-06-18 2003-11-18 Taiwan Semiconductor Manufacturing Company Dual layer photoresist method for fabricating a mushroom bumping plating structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649507B1 (en) * 2001-06-18 2003-11-18 Taiwan Semiconductor Manufacturing Company Dual layer photoresist method for fabricating a mushroom bumping plating structure

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