JPH03196625A - Dry etching - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dry etching method, and more particularly to a method for filling an opening with a polycrystalline silicon layer at high speed and with high controllability and reproducibility.

[Summary of the invention]

The present invention is a dry etching method for etchbacking a polycrystalline silicon layer formed by covering a base having an opening, in which the etchback is divided into two stages, and the process is performed until the base is exposed or just before it is exposed. The first etching step is a step in which a radical reaction proceeds using soil, and the subsequent etchback (over-etching) is performed to planarize the substrate surface. Either a deposition reaction and an etching reaction proceed competitively, or an ion-assisted reaction is performed. The second step in which
By using this etching process, it is possible to flatten the surface opening by filling the polycrystalline silicon layer without being affected by the so-called reverse loading effect.

Furthermore, the present invention uses a fluorine-based etching gas in the first etching step, and determines the end point of the first etching step by monitoring the emission spectrum of SiF, thereby forming the opening into a polycrystalline silicon layer. This makes it possible to perform a flat embedding process with high precision.

Furthermore, the present invention cleans the inside of the etching chamber in the first etching step, thereby eliminating contamination from residual deposits and ensuring a clean etching chamber even when a plurality of wafers are processed continuously in one etching chamber. This allows the process to proceed.

[Conventional technology]

In recent years, in the field of semiconductor devices such as VLSI and (JLSr), not only two-dimensional miniaturization but also three-dimensional integration has been progressing with the aim of achieving higher integration and higher performance, and multilayer wiring is being realized. Therefore, a hole-filling technique that flattens the surface of the substrate by burying contact holes and peer holes with a high aspect ratio with a conductive material is essential.This hole-filling technique includes methods such as selective tungsten method and blanket tungsten method. A method of embedding with polycrystalline silicon, or a method of embedding by depositing polycrystalline silicon and then etch-back has been proposed.

The method of filling with metal such as tungsten has the advantage that the resistance of the plug part itself is low and that it can be formed regardless of the conductivity type of the underlying diffusion layer. Difficult to secure
In addition, in the blanket tungsten method, tungsten and S
There is a problem that the adhesion with iO□ is low, and neither of them has reached a level suitable for mass production.

On the other hand, the method of embedding with polycrystalline silicon has disadvantages, such as the resistance of the plug itself being relatively high and the process lengthening as impurities must be introduced according to the conductivity type of the upper diffusion layer. This process has the advantage of being able to perform highly reliable processing. Moreover, Semiconductor World 1989 December
As reported in the Japanese issue, pages 103-105, in recent years, it has become possible to form low-resistance plugs using polycrystalline silicon by optimally selecting the ion species and implantation energy during ion implantation when introducing impurities. It is possible. Therefore, it must be said that filling the hole with polycrystalline silicon is more realistic at present.

Conventionally, for example, a contact hole formed in an insulating film,
In order to flatten polycrystalline silicon into the mouth of a pier hole, etc., the following method is used.

That is, as shown in FIG. 2(A), 1 is placed in advance on a conductive substrate (11) by a Stow or the like and has an opening (13).
A polycrystalline silicon layer (14) is formed to cover at least the opening (13).
is formed to substantially flatten the substrate surface.

Next, the polycrystalline silicon layer (14) is etched back. At this time, if the etch back is finished when the surface of the insulating film (12) is exposed, the opening (13)
) should be flatly buried by the polycrystalline silicon layer (14).

[Problem to be solved by the invention]

However, when actually etching back the polycrystalline silicon layer, the controllability of the remaining film thickness was poor, and the opening (1
3) is found to be difficult to achieve in a flat state buried by the polycrystalline silicon layer (14). For example, when a fluorine-based gas such as CFC is used as an etching gas, the uniformity, etching speed, reproducibility, etc. of the process are extremely good, but the polycrystalline silicon layer (14) on the insulating film (12) is removed. At the same time, the excess fluorine radicals concentrate in the opening (13). Therefore, as shown in FIG. 2(B), even a slight overetching causes the opening (13) that should originally become the plug part to
It is often experienced that the polycrystalline silicon layer (14) within the semiconductor substrate (14) is severely eroded and, in some cases, the semiconductor substrate (11) is also damaged. Since this is the opposite effect of the so-called loading effect (the etching rate locally increases), it is also called the reverse loading effect.

In order to prevent such a reverse loading effect, it is possible to use a chlorine-based etching gas as the etching gas, but there are still many problems.The chlorine-based gas has difficulty spontaneously etching the polycrystalline silicon layer. Ion bombardment can more effectively participate in the etching reaction.

Therefore, the etching rate is slow, and the progress of etching fluctuates due to the surface condition 9 of the polycrystalline silicon layer caused by ion bombardment or the presence of moisture, deposits, etc. in the etching chamber, and reproducibility tends to decrease.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a method for filling holes with a polycrystalline silicon layer at high speed and with high controllability and reproducibility.

[Means to solve the problem]

As a result of intensive studies to achieve the above object, the inventors of the present invention have found that etching immediately before the underlying layer is exposed or until a portion of the underlying layer begins to be exposed has a high etching speed, uniformity, and reproducibility. Proceed through a process that excels in
If the subsequent over-etching for flattening the substrate surface is performed using a process with excellent controllability of the remaining film thickness, the entire polycrystalline silicon layer can be etched at high speed with excellent uniformity, reproducibility, and controllability. I found out that it is possible. In this case, it is necessary to carefully determine the timing of etching switching based on the two types of processes.
The inventors have also discovered that this can be achieved by using a fluorine-based gas as the etching gas in the first half of the process and monitoring the emission spectrum of StF. moreover,
It has also been found that if the reaction for removing deposits in the etching chamber is performed simultaneously in the first half of the process, a clean process can always proceed even when processing multiple wafers in succession.

The present invention is proposed based on the above findings.

That is, the dry etching method according to the first aspect of the present invention is a dry etching method for etching back a polycrystalline silicon layer formed by covering a base having an opening, and mainly involves advancing a radical reaction. A first etching step in which the polycrystalline silicon layer is etched back until a part of the surface of the base is exposed or just before it is exposed, depending on the etching conditions; The method is characterized by comprising a second etching step in which etching is performed until the polycrystalline silicon layer is flatly buried in the polycrystalline silicon layer.

Furthermore, the dry etching method according to the second aspect of the present invention is a dry etching method for etching back a polycrystalline silicon layer formed by covering a base having openings, and mainly proceeds by a radical reaction. a first etching step in which the polycrystalline silicon layer is etched back until a part of the surface of the base is exposed or just before it is exposed under etching conditions; The method is characterized in that it includes a second etching step in which etching is performed until the polycrystalline silicon layer is flatly buried.

Furthermore, in the dry etching method according to the third aspect of the present invention, a fluorine-based etching gas is used in the first etching step, and the end point of the first etching step is determined by monitoring the emission spectrum of SiF. It is characterized by the fact that

Furthermore, the dry etching method according to a fourth aspect of the present invention is characterized in that the interior of the etching chamber is cleaned in the first etching step.

[Effect]

-1> In the etching reaction, various processes are complicatedly combined, such as a process that proceeds at high speed due to radical reaction, a process that involves deposition, and a process that proceeds at relatively low speed due to ion support. In a dry etching method for etching back a polycrystalline silicon layer, the etchback process is divided into two steps, a first etching process and a second etching process, and the advantages of the above process are utilized in each process. This is what was done. Hereinafter, the etching performed in the first and second etching steps will be referred to as first etching and second etching, respectively.

In the present invention, in the first etching step in which the underlying layer is etched back until it is exposed or just before it is exposed, conditions are adopted in which the radical reaction mainly proceeds. In this process, the main etching species are radicals such as fluorine radicals that are large enough to easily penetrate into the crystal lattice or grain boundaries of polycrystalline silicon, and cannot receive energy from the outside. Both react spontaneously with silicon and etch it.

Therefore, the first etching progresses at high speed and is less affected by moisture, deposits, etc. in the etching chamber, resulting in extremely excellent uniformity and reproducibility.

The present invention further provides conditions for etching to proceed at a slower rate in the second etching step in which etchback (overetching) is performed until the opening provided in the base is flatly filled with polycrystalline silicon. We are hiring. Such conditions are conditions that allow the deposition reaction and etching reaction to compete with each other in the first invention, and conditions that allow the ion-assisted reaction to proceed in the second invention. That is, in the first invention, the net etching rate is reduced by allowing the etching reaction to coexist with the deposition reaction, and in the second invention, the etching reaction is created in a system in which the etching reaction does not proceed spontaneously unless external energy is applied. In both cases, by reducing the etching rate, the remaining film thickness control property is improved. Therefore, in the second etching, the polycrystalline silicon N (plug part) buried inside the opening during over-etching is prevented from being rapidly etched away, and the flat hole can be filled with good reproducibility. It becomes like this. Although the second etching is slightly inferior in uniformity and reproducibility, in the present invention, most of the etchback is already performed using the first etching, which has excellent uniformity and reproducibility.
This is completed by etching, so there is virtually no problem.

By the way, the dry etching method of the present invention exhibits its maximum effect only when the end point of the first etching is accurately determined. Now, when a fluorine-based etching gas is used in the first etching process and the selectivity between the polycrystalline silicon layer and the underlying layer is sufficiently large and the first etching is started, the etching of the polycrystalline silicon layer progresses. During this period, volatile SiF is generated at a constant rate.

Therefore, when monitoring the emission spectrum of SiF at a wavelength of 440 nm, a peak of constant intensity is continuously observed. However, once a portion of the underlying layer begins to be exposed, the intensity of the above peak begins to decrease rapidly, and when the underlying layer is almost completely exposed, the peak intensity remains at a low level because the area to be etched decreases. , the end point is the point where it stays at this low level,
In the case of the present invention, this is too late, so the end point is defined as the point at which the peak intensity begins to decrease. This point can be determined by suitable electrical signal processing methods such as second order differentiation.

Further, according to the present invention, if the etching gas system for each etching step is appropriately selected, it is also possible to clean the inside of the etching chamber in the first etching step. This cleaning effect is extremely significant when continuous processing is performed on a plurality of wafers. That is, in the second etching step, depending on the type of etching gas used, carbon-based or silicon-based polymers may remain in the etching chamber, but in the first etching step, there is a possibility of a deposition reaction. In particular, if a reduced etching gas system is used, the radical species generated during this process will efficiently convert residual deposits into volatile substances and remove them, making it possible to always proceed with a clean process. .

Therefore, the dry etching of the present invention can be performed at high speed as a whole with high uniformity and reproducibility.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

Example 1 This example is an example in which the first and third aspects of the present invention are applied, and polycrystalline silicon is flattened into an opening formed in an insulating film. This process will be explained with reference to FIGS. 1(A) to 1(C).

First, as shown in FIG. 1(A), an insulating film (2) made of silicon oxide, for example, is formed on a semiconductor substrate (1) made of silicon or the like, and patterned to form an opening (3). Next, a polycrystalline silicon layer (4) is deposited on the entire surface using a vacuum thin film forming technique such as CVD, which has excellent coverage, and the surface of the base is substantially flattened.

Next, as a first etching process, polycrystalline silicon N(4) is etched.
etching was done. The first etching is performed using a high-frequency bias application type ECR (electron cyclotron resonance) etching device, and the conditions are, for example, SF,
Flow rate 30 SCCM, C1Cl! 5F3 (Freon 11
3) Flow fi305CCM, gas pressure 10mTorr
.

Microwave power 850W, high frequency bias 30W
And so. In this step, a reaction using fluorine radicals as the main etching species progressed, the etching rate was as fast as 6000 persons/min, and the uniformity was good at around ±2%. Also, during this etching, SiF at a wavelength of 440 nm
The intensity of the emission spectrum was continuously monitored, and the point at which the intensity began to decrease was defined as the end point of the first etching. At this time, the base body is as shown in FIG. 1(B).
The insulating film (2) was exposed in some places on the surface of the substrate.

Next, a second etching process was performed to flatten the surface of the substrate. This condition is, for example, SF.

Flow 175CCM, C yo C15F3 < Freon 113)
Flow rate 535CCM, gas pressure 10+5Torr, microwave power 850W.

The high frequency bias was set to 100W. The etching gas used here had the same components as the one used in the first etching, but the flow rate ratio was changed to deposit carbon-based polymers such as C and CZ.

F. is increased. As a result, conditions were achieved in which the etching reaction and the deposition reaction competed, and 2,000 people/
At a relatively slow etching speed of 1 minute, the uniformity was ±5
%, and as shown in FIG. 1(C), the surface of the substrate was extremely well planarized.

In this case, the etching rate is reduced to 94% of the remaining film thickness.
Since the corrosion resistance was improved, the plug portion (4a) inside the opening (3) was not eroded. Note that this second
The etching rate and uniformity of the second etching seem to be lower than the first etching, but since the purpose is to over-etch after most of the etching has already been completed, there is no practical problem, and the process as a whole is is achieved with sufficient speed and uniformity.

Incidentally, the etching gas used in each etching step can be selected from a wide range of materials as long as it can achieve the desired conditions. However, as mentioned above, if a mixed etching gas consisting of the same components is used in both etching processes and the reaction mode in each process can be switched simply by changing the flow rate ratio, an extremely practical dry etching method can be obtained. Served. In this case, in addition to the above-mentioned SF, NF3. CI! , Fl, etc., and gases that can deposit carbon-based polymers include the above-mentioned 0) Cz
ClxFx (707113) (7) Other Ct Cl
NF4 (Freon 114), CHF1. CIIzFz,C
H,lFCz F b , C3F m , Ca
F+. ,CC1,,CC1,F.

CCf!　z　F　! etc. can be used.

If a deposition gas like that used in this embodiment is used, deposits such as carbon-based polymers remain in the etching chamber after the second etching is completed, and this causes contamination. At first glance, it appears that a decrease in reproducibility occurs when continuous processing is carried out indoors. However, in the first etching step, most of the remaining deposits are converted into volatile substances by fluorine radicals and removed, so that a clean process can be carried out at all times.

Example 2 In this example, the same embedding as in Example 1 described above was performed by applying the second and third aspects of the present invention. That is, after carrying out the first etching in the same manner as in Example 1 to bring the substrate into the state shown in FIG. It was +11. This condition is, for example, BClx fLfi130 SCCM, Cj! The flow rate was 20 SCCM, the gas pressure was 10 mTorr, the microwave power was 850 W, and the high frequency bias was 100 W. As a result of this etching, an opening (3) is formed at the plug portion (4a) of the polycrystalline silicon layer, as shown in FIG.
) could be embedded flatly.

Example 3 In this example, the same embedding as in the above-described example was performed by applying the second and fourth aspects of the present invention.

First, the first etching was performed using SF and gas alone, and the substrate was brought into the state shown in FIG. 1(B). The conditions at this time are
For example, S F h '/li'lt 60 SCC row, gas pressure 10 *Torr+ microwave power +11
50 W and a high frequency bias of 100 W.

Next, as a second etching, etching was performed under the same conditions as in Example 2, and as shown in FIG. 1(C), the opening (3
I was able to embed the tube flatly.

Here, in the first etching step, as in Example 1 or Example 2, Cz Cl 3 F! The reason SF was used alone without being used in conjunction with SF was to enhance the cleaning effect in the etching chamber during the first etching step. That is, when a B Cl s / Cl z -based mixed gas is used in the second etching step, the etching reaction product S i Clm reacts with oxygen released from the quartz member in the etching chamber. Sin was produced as a by-product.

may also form residual deposits. Therefore, it is more effective to perform the first etching under conditions that eliminate the possibility of deposition as much as possible. As a result, even in continuous processing, an extremely clean process proceeded with good reproducibility.

In each of the above-mentioned examples, the composition or flow rate ratio of the etching gas used is changed between the first etching process and the second etching process, but due to changes in other conditions, the radical reaction It is also possible to switch between the process and the process mainly based on ion-assisted reactions. In general,
If the gas pressure is set high and the radio frequency bias is set low, a process based on radical reactions can proceed, and conversely, when the gas pressure is set low and the radio frequency bias is set high, a process based on ion-assisted reactions can proceed.

Further, although each of the above-mentioned embodiments assumes filling of contact holes and peer holes with polycrystalline silicon, the present invention is not limited to these embodiments.
For example, the present invention can be similarly applied to the case where a capacitor is formed by filling a trench formed in a single crystal silicon substrate with polycrystalline silicon via a thin insulating layer.

〔Effect of the invention〕

As is clear from the above description, if the present invention is applied, the etchback of the polycrystalline silicon layer formed by covering the base having the opening can be divided into two stages, thereby reducing the influence of the so-called reverse loading effect. It becomes possible to quickly and flatly fill the opening with the polycrystalline silicon layer without causing damage. Moreover, since the radical reaction mainly proceeds during the initial etchback, a clean and highly reproducible process always proceeds even in continuous processing. Therefore, if the dry etching method of the present invention is applied to the manufacture of semiconductor devices, it is possible to provide semiconductor devices with a high degree of integration and high reliability with high productivity and yield.

[Brief explanation of drawings]

FIGS. 1(A) to 1(C) are schematic cross-sectional views illustrating an example of the dry etching method of the present invention according to the process order, and FIG. 1(A) shows an insulating film, an opening, and a polycrystal. The process of forming a silicon layer, FIG.
FIG. 2(C) shows the process of forming the plug part by the second etching. FIGS. 2(A) and 2(B) show the problems in the conventional general etch-back process for polycrystalline silicon layers. These are schematic cross-sectional views for explanation, and FIG. 2(A) shows the formation process of the insulating film, opening, and polycrystalline silicon layer, and FIG. 2(B) shows the state of erosion inside the opening after etchback. show. ■...Semiconductor substrate 2...Insulating film 3...Opening part 4...Polycrystalline silicon layer 4a...Plug part

Claims (4)

[Claims] (1) In a dry etching method for etching back a polycrystalline silicon layer formed by covering a base having openings, a part of the surface of the base may be exposed or A first etching step in which the polycrystalline silicon layer is etched back until just before it is exposed, and the opening is flatly buried in the polycrystalline silicon layer due to conditions that allow the deposition reaction and the etching reaction to compete. A dry etching method comprising a second etching step of performing etch back up to the point where the dry etching process is performed. (2) In a dry etching method for etching back a polycrystalline silicon layer formed by covering a base having openings, a part of the surface of the base is exposed or a first etching step in which the polycrystalline silicon layer is etched back until just before it is exposed; and a first etching step in which the polycrystalline silicon layer is etched back until the opening is flattened by the polycrystalline silicon layer using etching conditions that mainly promote ion-assisted reaction. A dry etching method comprising a second etching step of performing back etching. (3) A fluorine-based etching gas is used in the first etching step, and the end point of the first etching step is determined by monitoring the emission spectrum of SiF. Dry etching method described. (4) The dry etching method according to any one of claims 1 to 3, wherein the first etching step includes cleaning the inside of the etching chamber.