JPH03201037A - Lsi test system - Google Patents

Abstract

PURPOSE:To perform various tests without adding the exclusive hardware and terminals by storing previously a test program into an LSI. CONSTITUTION:In a through-pass function test mode, a program for through-pass function test is read out of a ROM 5 via a CPU 3. Then the data inputted through an input terminal 1 and stored in a buffer 2 are read out and stored in a buffer 7 as they are. Then the data are outputted to an output terminal 11 from the buffer 7. In regard of another example of the text program, the arithmetic operations including the addition, the subtraction, the multiplication, the division, etc., are carried out via a memory 4 and an arithmetic processing unit 6 to the data inputted through a bidirectional input/output terminal 10 and stored in a buffer 9. Then the normalcy of an internal arithmetic processing function can be tested and confirmed. Thus, other various tests can be easily carried out without increasing the hardware quantity and the number of pins.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an LSI testing method, and more particularly to an LSI testing method suitable for application to LSIs such as one-chip microprocessors.

One example of a test method to check whether a conventional LSI is correctly mounted on a package is to control all the pins of the LSI and check that the output pin changes according to the function of each pin. There is.

However, with this method, as LSIs become more sophisticated and highly integrated, the number of test patterns that must be supplied to the input terminals that control the output terminals of the LSIs to both "1" and "0" levels becomes enormous. This results in a complex pattern and requires a large amount of time to develop.

Therefore, a slew bus test is used as a method to easily confirm that the LSI is correctly mounted on the package. A circuit block of an LSI having this through bus test function is shown in FIG.

Each input signal from the input terminals 21 to 24 of the LSI is manually input to the logic circuit section 31 via manual buffers 25 to 28, respectively. This logic circuit section 31 generates and outputs an output signal corresponding to an input signal.

These output signals are the human power (A) of the selection circuits 32-35, and the outputs of the human power buffers 25-28 are applied to the human power (B). The respective outputs of these selection circuits 32-35 are led out to three output terminals 36-3 of the LSI.

A switching instruction signal between the normal mode and the through bus test mode is supplied to the input terminal 29 of the LSI and introduced into the manual buffer 30 . The output of this manual buffer 30 is applied to the selection signal terminal (S) of each selection circuit 32-35.

In the normal mode, each of the selection circuits 32 to 35 operates to select each output of the logic circuit section 31, so that each of the output terminals 36 to 3 corresponds to a signal applied to the input terminals 21 to 24, respectively. It is now possible to obtain an output signal that is

On the other hand, during the through bus test, each of the selection circuits 32 to 35 operates to select each output of the manual buffers 25 to 28, respectively, so that each of the output terminals 36 to 39 is connected to each input terminal 21.
The signals applied to 24 to 24 are output as they are.

In such a conventional LSI, when performing a through-bus test, a test-dedicated circuit such as selection circuits 32 to 35 is required to selectively derive normal logic signals and through-bus signals inside the LSI. In addition, two switching signal input terminals are required for switching between the normal mode and the LSI through-bus test mode.

For this reason, with conventional LSIs, it is necessary to add dedicated hardware to perform through-pass tests, and the LSI
The disadvantage is that the gate size of the LSI increases, and the amount of heat generated by the LSI also increases accordingly.

Further, there is a drawback that a mode switching signal input terminal is required, which increases the number of terminals of the LSI, and the case shape of the LSI may become large, which is inconvenient.

OBJECTS OF THE INVENTION An object of the present invention is to provide an LSI testing method that allows not only through-pass testing but also various other tests to be easily performed without increasing hardware or increasing the number of pins.

Structure of the Invention According to the present invention, there is provided a test method for an LSI including a program storage memory storing a program and a processor that performs processing according to the program, wherein a test program is stored in the program storage memory. There is obtained an LSI testing method characterized in that the test program is activated in response to a test command and the processor is controlled so as to derive an input signal from an input terminal as it is to a predetermined output terminal.

Further, according to the present invention, there is provided an LSI testing method including a program storage memory storing a program, a processor that performs processing according to the program, and an arithmetic processing means whose operation is controlled by the processor, wherein the program storage memory A test program is stored in the test program, the test program is activated in response to a test command, the signal from the input terminal is processed by the calculation processing means, and the processing output is derived to a predetermined output terminal. An LSI testing method is obtained, which is characterized in that the processor is controlled in this manner.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention,
For example, it is equivalent to a general functional block diagram of a one-chip microprocessor. That is, an input buffer 2 receives a serial input signal from a serial input terminal 1;
A CPU 3 that controls the operation of the system, a memory 4, a ROM 5 for storing programs, and an ALU that has arithmetic functions.
(arithmetic processing unit) 6, an output buffer 7 for deriving a serial output signal to the serial output terminal 11, an output buffer 8 for deriving a parallel output to the bidirectional parallel terminal 10, and receiving a parallel input signal from the bidirectional parallel terminal 10. It is configured to include an input buffer 9 and an internal bus 13.

In such a configuration, in response to the reset manual power applied from the input terminal, the CPU 3 resets the read address of the ROM 5 in which the program is stored to address 0, and also resets the read address of the ROM 5 in which the program is stored to address 0. The operating mode instruction signal stored in the operating mode instruction signal is determined.

Here, if it is determined that the mode is normal operation mode, the CPU
3 sequentially reads out necessary programs stored in the ROM 5, while controlling the memory 4 and ALU 6 to execute desired data processing.

If it is determined that the mode is through-pass function test mode, the CP
By U3, through-pass function test programs stored in advance in the ROM 5 are sequentially read out. For example, the program may be a program that executes a series of processes of reading data input from the input terminal 1 and stored in the buffer 2, storing it in the buffer 7 as it is, and deriving it to the output terminal 11.

Another example of the test program is a series of reading data input from the bidirectional input/output terminal 10 and stored in the buffer 9, storing it in the buffer 8 as it is, and deriving it to the bidirectional input/output terminal 10. It may be a program that executes processing.

Furthermore, as another example of the test program, the buffer 9
Performs arithmetic processing such as addition, subtraction, multiplication, and division on the data stored in the memory 4 and ALU 6 to test not only the through bus function but also the normality of the internal arithmetic processing function. You can also do In addition, input terminal 1
It is also possible to apply similar arithmetic processing to the data input from the input terminal 11 and to output the data to the output terminal 11.

Effects of the Invention As described above, according to the present invention, by storing a test program in the LSI in advance, and by starting this program at the time of testing and testing the LSI, it is possible to perform the LSI test by simply adding firmware. Various tests can be performed, and there is no need to add dedicated /\-ware or terminals.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention. FIG. 2 is a system block diagram illustrating the prior art. Explanation of symbols of main parts 1... Input terminal 3... CPU 5... ROM 10... Bidirectional terminal 11... Output terminal 12 ...Reset input terminal

Claims (2)

[Claims] (1) A program storage memory that stores a program;
A processor that performs processing according to this program.
This is an SI test method, in which a test program is stored in the program storage memory, the test program is activated in response to a test command, and the input signal from the input terminal is directly output to a predetermined output terminal. An LSI testing method characterized in that the processor is controlled as follows. (2) a program storage memory storing the program;
L includes a processor that performs processing according to this program, and arithmetic processing means whose operation is controlled by the processor.
In this SI test method, a test program is stored in the program storage memory, the test program is started in response to a test command, and the signal from the input terminal is processed by the arithmetic processing means. 1. A testing method for an LSI, characterized in that said processor is controlled to derive an arithmetic processing output from said processor to a predetermined output terminal.