JPH04155278A - Lsi tester - Google Patents

Abstract

PURPOSE:To enable a test closer to a condition of a customer's use by creating operation on a machine which packages a single-chip microcomputer to be tested and then achieving with an LSI tester. CONSTITUTION:A single-chip microcomputer to be tested 6 is connected by an I/O circuit 5 and an external control circuit 7 and then single-chip microcomputer I/O signals 11 and 12 on a packaging machine 13. Also, the I/O signals 11 and 12 of the single-chip microcomputer and tester terminals 8 and 7 are connected and then the single-chip microcomputer 6 allows a signal during operation to be inputted to a memory circuit part 2 by a built-in program. Information which is inputted to a memory circuit 2 is edited to a test pattern through a test pattern editing circuit 3 and is stored into a memory part 4, thus enabling operation test to be performed according to test pattern information of the memory part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI tester, and more particularly to an LSI tester that performs an operational function test of an LSI that incorporates a customer's program, such as a single-chip microcomputer.

[Conventional technology]

With the development of semiconductor technology, the demand for microcomputers is increasing at an accelerating pace, but on the other hand, the development of testers for them has become a problem.

Today, all semiconductor circuit devices (hereinafter referred to as LSI) are LS
The I tester is activated by a directly input test pattern, and its output pattern is compared and verified with an expected value to determine whether it is good or bad.

[Problem to be solved by the invention]

However, when trying to test a microcomputer using a conventional LSI tester, this LSI usually requires several to dozens of test patterns just for the execution of one instruction, and these test patterns are not processed through logic simulation etc. on a large computer. Created.

However, since single-chip microcomputers and the like have built-in customer programs, operational tests using built-in programs are not normally carried out because it is difficult to prepare test patterns for each customer.

An object of the present invention is to provide an LSI tester that can easily perform operational tests using built-in programs.

[Means to solve the problem]

The LSI tester of the present invention includes a memory circuit section that stores input/output terminal information of the LSI during actual operation in synchronization with a predetermined signal from a device equipped with the LSI under test, and information stored in the memory circuit section. The test pattern editing circuit is configured to include a test pattern editing circuit for editing test patterns.

〔Example〕

FIG. 1 is a block diagram of a first embodiment of the present invention.

The LSI tester 1 includes a memory circuit section 2, a test pattern editing circuit 3, and a test pattern memory section 4, which are connected to each other, and tester terminals 8.9 are connected to the memory circuit section 2 and the test pattern memory section 4.

A single-chip microcomputer 6 to be tested is connected to an input/output circuit 5 and an external control circuit 7 on a mounting machine 13 by single-chip microcomputer input/output signals 11 and 12.

In addition, the input/output signals 11.12 of the single-chip microcomputer and the tester terminals 8.9 are connected, and the mounting machine 13
Above, the single-chip microcomputer 6 under test is operating according to the built-in program, and the signal is sent to the tester terminal 8.9.
The signal is inputted to the memory circuit section 2 of the LSI tester 1 through the.

The information input to the memory circuit section 2 is edited into a test pattern through the test pattern editing circuit 3 and stored in the test pattern memory section 4. Therefore, an operation test using the built-in program of the single-chip microcomputer 6 under test can be performed using the test pattern information in the test pattern memory section 4.

FIG. 2 is a block diagram of a second embodiment of the invention.

Single-chip microcomputer input/output signals 11
．． 12 is the tester terminal 8. The only difference from the first embodiment described above is that the test pattern is directly input to the test pattern memory section 4 through the test pattern editing circuit 3.

The single-chip microcomputer 6 under test stores a test pattern in the test pattern memory section 4 based on the signals that are being operated by the built-in program, and the operation test can be executed by the built-in program.

〔Effect of the invention〕

As is clear from the above description, it is possible to easily perform a test in which the LSI tester realizes exactly what is running on the mounting machine of the single-chip microcomputer under test.

Therefore, it is possible to extremely quickly create a test pattern, which would require a long time using a large computer for each customer's program, in the conventional tester, and it is also possible to perform tests that are close to the customer's usage conditions, thereby improving the quality of the test.

Although the tester according to the present invention has been described by way of example of testing a single-chip microcomputer, it is not limited to single-chip microcomputers and can be applied to testing other LSIs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the invention, and FIG. 2 is a block diagram of a second embodiment of the invention. 1.1a...LSI tester, 2...memory circuit section,
3... Test pattern editing circuit, 4... Test pattern memory section, 5... Input/output circuit, 6... Single chip microcomputer, 7... External control circuit, 8
．． 9... Tester terminal, 10... Test pattern output, 11.12... Input/output signal, 13... Mounting machine.

Claims (1)

[Claims] A memory circuit section for storing input/output terminal information of the LSI under test during actual operation of the LSI under test in synchronization with a predetermined synchronization signal, and editing the information stored in the memory circuit section into a test pattern. An LSI tester comprising a test pattern editing circuit.