JPH03201152A - Prefetch control system - Google Patents

Abstract

PURPOSE:To reduce the generation of data overrun by extending a data requirement interval used for the prefetch of write data, and during the period of prefetch, suppressing that the same channel executes a data request at a data transfer speed more than required speed. CONSTITUTION:A write data prefetching operation display means 11 turns on a write data prefetch display signal 23 for displaying the prefetch operation of write data 27 and outputs the signal 23 to a masking means 14 and a timer means 12 outputs a time-out signal 20 at every fixed period. A data request effective FF 13 is set up by the time-out signal 20 and reset by a replay signal 26 outputted from a channel control part 2, and if the FF 13 is in the reset state when the prefetching execution of the write data 27 is displayed, the masking means 14 masks a data requiring signal 24 and suppresses the transfer speed of the write data 27 to a prescribed value or below. Consequently, the waiting time of a data requirement from another channel which is not the prefetching of the write data 27 can be shortened and the generation of data overrun can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and more particularly to a prefetch control method for controlling the data transfer rate when prefetching write data in a data transfer device.

[Conventional technology]

Conventionally, in this type of data transfer device, a large amount of data buffer is provided in the channel to prevent data overruns, and when transferring write data, the write data is first read into the data buffer and then transferred to the input/output (I10) interface. However, the data transfer speed to the channel during the prefetching of write data was performed at the maximum transfer capacity of the channel.

(The invention attempts to solve this problem! 1113) In the conventional data transfer device described above, data was transferred at maximum capacity during the prefetching of write data until the data bath sofa was full. If this happens in multiple channels at the same time, the processing of the channel control unit will be exclusive to these channels, and data requests (both read and write) from other channels will have to wait for a long time. There is a drawback that data overrun occurs.

In view of the above-mentioned points, an object of the present invention is to lengthen the data request interval of a channel during prefetching of write data, so that the same channel does not execute data requests at a data transfer rate higher than necessary while prefetching write data. In this way, it is an object of the present invention to provide a prefetch control system that reduces the occurrence of data overruns by shortening the waiting time for data requests from other channels that are not currently prefetching write data.

[Means to solve the problem]

The preemption control method of the present invention provides a data transfer device that includes a plurality of channels that control input/output interfaces and a channel control unit that multiplexes control of the plurality of channels, in which the channel indicates that write data is being preempted. write data prefetching display means; timer means for outputting a timeout signal at regular intervals; and data request valid display means that is set by the timeout signal from the timer means and reset by a reply signal from the channel control section; When the write data prefetching display means indicates that write data is being prefetched and the data request valid display means is in a reset state, the data request signal to the channel control unit is masked to reduce the write data transfer rate. masking means for suppressing the value to below a predetermined value.

[Effect]

In the prefetching control system of the present invention, the write data prefetching display means displays that the write data is being prefetched, the timer means outputs a timeout signal at regular intervals, and the data request valid display means responds to the timeout signal from the timer means. is set and reset by a reply signal from the channel control unit, and if the masking unit is in the write data prefetching display unit and the write data prefetching display unit is indicating that the data request valid display unit is in the state, the channel control unit The data request signal for the write data is masked to suppress the write data transfer speed to a predetermined value or less.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data transfer device to which a preemption control method according to an embodiment of the present invention is applied. This data transfer device includes a main memory 1, a channel control unit 2 connected to the main memory 1, a plurality of channels 3 connected to the channel control unit 2, and a peripheral device 4 connected to the channel 3. Its main parts are composed of:

The channel 3 includes a buffer control unit 10, a write data prefetching display means 11, a timer means 12, and a data request valid flip-flop 1 which is a data request valid display means.
3 and mask means 14.

The buffer control unit 1O has a built-in data buffer, and stores write data 27 in the data buffer in response to a reply signal 26 from the channel control unit 2 in response to the data request signal 24. Further, the buffer control unit 10 controls I1
0 interface 28 to and from peripheral device E4.

The write data prefetching display means 11 is set and reset by the cent/reset signal 21 from the buffer M control unit 10, and is masked by turning on the write data prefetching display signal 23 that indicates that the write data 27 is being prefetched during cents. Output to means 4.

The timer means 12 outputs a timeout signal 20 at regular intervals.
is output to the data request valid flip-flop 13.

The data request valid flip-flop 13 is connected to the timer means 1.
It is sent by the timeout signal 20 from the channel control section 2, and reset by the reply signal 26 from the channel control section 2. At the time of sending, the data request valid signal 22 is turned on and outputted to the masking means 14.

The masking means 14 displays the write data prefetching display means 11.
While the write data prefetching display signal 23 from the data request valid flip-flop 13 is on, if the data request valid signal 22 from the data request valid flip-flop 13 is on, the buffer control unit lO
The data request signal 24 from the buffer controller 10 is output as a data request signal 25 to the channel controller 2, and if the data request valid signal 22 is off, the data request signal 24 from the buffer controller 10 is masked.

Next, the operation of the preemption control system configured as described above will be explained.

First, when the channel control unit 2 instructs the channel 3 to transfer write data (data transfer from the main memory 1 to the peripheral device 4), the buffer control unit 10 causes the write data prefetching display unit 11 to be displayed by the set/reset signal ε 21. Then, the write data prefetch display signal 23 is turned on, and a write data request is made to the masking means 14 using the data request number 18 24.

The masking means 14 includes a write data prefetching display means 1.
Since the write data prefetching display signal 23 from 1 is on and the data request valid signal 22 from the data request valid flip-flop 13 is on due to the timeout signal 20 from the timer means 12, the data request signal 24 is output to the channel control section 2 as a data request signal 25.

Channel control unit 2 reads data from main memory l in response to data request signal 25, outputs it as write data 27 to buffer control unit 10, and outputs reply signal 26 to buffer 1ti11111 unit 10 and data request valid flip-flop 13. do.

Data request valid flip-flop 13 is reset by reply signal 26 to turn data request valid signal 22 off.

The buffer control unit 1O stores the write data 27 in an internal data buffer in response to the reply signal 26, and if there is space in the data buffer, re-outputs the data request signal 24 to request the next data.

However, at this point, the data request valid flip-flop 13 is reset and the data request valid signal 22 is turned off, so the masking means 14 outputs the data request signal 25 despite the input of the data request signal 24. mask.

After this, when a time shorter than the predetermined timeout interval of the timer means 12 has elapsed, the timer means 12
always generates a timeout, and the timeout signal 2
0 is turned on.

Therefore, the data request valid flip-flop 13 is set again by the timeout signal 20, and the data request valid signal 22 is turned on.

As a result, the masking means 14 requests the data (No. 8 24
is output to the channel control section 2 as a data request signal 25.

The channel 1111m unit 2 reads data from the main memory l in response to the data request signal 25, and writes the write data 27.
is input to the buffer control unit 10 as a reply signal 26.
is output to the buffer control unit 10 and the data request valid flip-flop 13.

The data request valid flip-flop 13 is reset again by the reply signal 26 and remains off until the timer means 12 times out.

The buffer control unit 10 takes the write data 27 into the data buffer in response to the reply signal 26, and continues to repeatedly output the data request signal 24 until the data buffer is full.

The masking means 14 outputs the data request signal 24 to the channel control section 2 as a data request signal 25 after waiting until the data request valid signal 22 is turned on.

Thereafter, similar processing is repeated, and when the data buffer is full and prefetching of write data is completed, the buffer control unit 1G resets the write data prefetching display means 11 by the cent/reset signal 21, and transfers the I10 ink from the data buffer. Transfer of write data to the peripheral device 4 via the interface 28 is started.

Around light data! When the transfer to Jlf4 progresses and a certain amount of space becomes available in the data buffer, the buffer control unit 10 again transmits the data request signal 24 to the masking unit 14.
Output for.

Since the write data prefetching display signal 23 is off, the masking means 14 outputs the data request signal 24 as the data request signal 25 to the channel control unit 2 regardless of whether the data request valid signal 22 is on or off.

When the reply signal 26 is returned, the buffer control unit 10 takes in the write data 27 into the data buffer.

Similarly, while transferring write data to and from the peripheral device 4, the buffer control unit 10 outputs a data request signal 24 every time a certain amount of space becomes available in the data buffer, thereby executing the data transfer operation. .

〔Effect of the invention〕

As described above, the present invention includes a write data prefetching display means, a timer means, a data request valid display means, and a masking means, and increases the data request interval during write data prefetching. By preventing the same channel from executing data requests at a data transfer rate higher than necessary, it is possible to shorten the waiting time for data requests from other channels that are not preempting write data and reduce the occurrence of data overruns. There is an effect that it can be done.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a data transfer device to which a preemption control method according to an embodiment of the present invention is applied. In the figure, l... Main memory, 2... Channel control unit, 3... Channel, 4... Peripheral device, 10... Buffer control unit, 11... Write data prefetching display means, 12...・Timer means, 13...Data request valid flip-flop (data request valid display means), mask means, timeout signal, set/resen ■δ number, data request valid signal, write data prefetching display signal, data request signal, data These are the request signal, reply signal, write data, and I10 interface. l 4 ・ 20 ・ 2 l ・ 22 ・ 23 ・ 24 ・ 25 ・ 26 ・ 27 ・ 28 ・ Figure 1

Claims (1)

[Scope of Claims] A data transfer device comprising a plurality of channels for controlling input/output interfaces and a channel control section for multiplexing control of the plurality of channels, wherein the channel is configured to transmit write data indicating that write data is being prefetched. Pre-fetching display means; timer means for outputting a timeout signal at regular intervals; data request valid display means set by the timeout signal from the timer means and reset by a reply signal from the channel control section; When the data prefetching display means indicates that write data is being prefetched and the data request valid display means is in a reset state, the data request signal to the channel control unit is masked and the write data transfer rate is set to a predetermined value. A preemptive control method characterized by having a masking means for suppressing: