JPH03201720A - Timing signal extraction circuit - Google Patents

Abstract

PURPOSE:To eliminate the need to incorporate an oscillation circuit in the device by controlling a reference clock signal synchronously with a reception signal by a delay quantity only. CONSTITUTION:Assuming that the phase difference between a reception signal A being an input signal of a phase comparator 1 and a reference clock signal B as phi1, then the phase difference signal from the phase comparator 1 is a voltage depending on the phase difference. Moreover, a low pass filter 2 outputs a voltage D being a value of (v) resulting from integrating the voltage of a phase difference signal C. Thus, a voltage controlled delay circuit 3 obtains a delay clock signal E synchronously with the reception signal together with the phase matching by providing a delay phi2 with respect to a reference clock A by the input voltage 2. Thus, it is not required to integrated an oscillation circuit in its inside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing signal extraction method for generating tarock using a digital received signal transmitted through a transmission line.

[Conventional technology]

Conventionally, this type of timing signal extraction method includes a clock regeneration method using a timing tank using an LC or various filters, a clock generation method using a PLL circuit, and the like.

[Problem to be solved by the invention]

In the conventional timing signal extraction method described above, for example, the one using a timing tongue using a filter, it is difficult to miniaturize the filter itself, and it is manufactured using a manufacturing technology different from that of semiconductor integrated circuits. It is difficult to integrate and integrate peripheral circuits into one chip. Also, P.L.
Those using L circuits have an oscillating circuit in the circuit, so
The frequency that can be synchronized is determined by the oscillation frequency range of this oscillation circuit. Therefore, synchronization with a high-speed clock has some restrictions on the circuit, and in addition, in a PLL circuit, the oscillation circuit output is divided and used in order to ensure stability, so a high-frequency oscillation circuit is required to synchronize with the high-speed clock. It is necessary to configure a large number of devices, which is a factor that hinders integration.

[Means to solve the problem]

The timing signal extraction method of the present invention includes a delay means for outputting a reference clock signal delayed according to a voltage value of a control signal, and a phase difference signal according to a phase difference between the reference clock signal and a received signal. It has a phase comparison means and an integration means for outputting the control signal obtained by integrating the phase difference signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a signal waveform diagram for explaining the operation of the first embodiment.

In FIG. 1, a phase comparator 1 compares a received signal A with an internal reference clock signal B and outputs a phase difference signal C. The low-pass filter 2 outputs a voltage value obtained by integrating the phase difference signal C output from the phase comparator 1. The voltage-controlled delay circuit 3 delays the reference clock signal B according to the voltage value from the low-pass filter 2 and outputs it as a delayed clock signal E.

Next, to explain the operation with reference to FIGS. 1 and 2, if the phase difference between the received signal A, which is the input signal of the phase comparator 1, and the reference clock signal B is φ■, then the phase comparison The phase difference signal C from the device 1 outputs a voltage determined by the phase difference. Furthermore, in the low-pass filter 2, the phase difference signal C
It outputs the voltage value V, which is the integral of the voltage. By applying a delay of φ2 to the reference clock A using the input voltage value 2, the voltage-controlled delay circuit 3 can obtain a delayed clock signal E that is synchronized with the received signal including its phase.

FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a signal waveform diagram for explaining the operation of the second embodiment.

First, in FIG. 3, the received signal a and the output signal f of this circuit are input to the phase comparator 11, and the phase difference comparison result d is
is converted to Further, the output e integrated by the low-pass filter 12 becomes a control input of a voltage-controlled delay circuit 13 that provides a delay with respect to the reference clock b, and a delayed clock signal f is output.

Next, to explain the operation, the input reference clock signal S is given a delay amount of initial value φ1 to the voltage-controlled delay circuit 1.
3 outputs the delayed clock signal f, the phase comparator 11 outputs a voltage VC corresponding to the phase difference φ2 between the delayed clock f and the received signal a. According to the control voltage e from the low-pass filter 3 that integrates this Vc, the delay amount of the voltage-controlled delay circuit 13 becomes φ'l, and the received signal a
The phase difference between the delay clock e and the delayed clock e is φ'2. Thereafter, by repeating this procedure and performing control so that the phase difference between the received signal a and the delayed clock f is minimized, it is possible to obtain the delayed clock output f whose phase is synchronized with the received signal a.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for an internal oscillation circuit by controlling the reference clock signal synchronized with the received signal only by the amount of delay, and the phase accuracy does not depend on the original oscillation frequency. It is also easy to integrate circuits and has the effect of reducing costs.

The block diagrams of the embodiments, FIGS. 2 and 4 are signal waveform diagrams for explaining the operations of the first and second embodiments.

1.11... Phase comparator circuit, 2.12... Low pass filter, 3,13... Voltage controlled delay circuit.

Claims (1)

[Claims] a delay means for outputting a reference clock signal delayed according to a voltage value of a control signal; a phase comparison means for outputting a phase difference signal according to a phase difference between the reference clock signal and the received signal; and the phase difference signal. and integrating means for outputting the control signal obtained by integrating the timing signal.