JPH03210646A - Direct memory access device - Google Patents

Abstract

PURPOSE:To substantially prevent the deterioration of the transfer speed of its own data request signal DRQ and also to evade the hindrance of transfer of the lower rank direct memory access DMA by inputting the DRQ of the lower rank DMA and gating its own DRQ. CONSTITUTION:A memory 7 and plural I/O devices 8a - 8c having the priority for transfer of data are provided together with plural DMA channels which have the priorities and connects a DMAC which controls the transfer of data on the memory 7 and the devices 8a - 8c to an I/O bus. In this case, the next DRQ of its own is not outputted until the DRQ of a lower rank DMA is accepted by gating the DRQ of a DMA channel of its own with the DRQ received from the lower rank DMA channel when the DRQ of the lower rank DMA requires the service. Thus the deterioration of its own DMA transfer speed is substantially prevented without hindering the working of the lower rank DMA channel.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to direct memory access (hereinafter abbreviated as DMA) that connects to an I/O bus having DMA channels with multiple priorities and performs DMA transfer. It is related to the device.

[Conventional technology]

FIG. 3 shows a block diagram of a computer that performs DMA transfer.

In the figure, (4) is the CPU, (5) is the I/O bus that transfers data between the CPU and peripheral devices, and (6) is the DMAC (D-^ controller) that controls DMA.
, (7) is a memory for storing data, (8a) to (8C
) is an I/O device that transfers data between a computer and other devices.

Next, the operation will be explained. DMA transfer is a direct memory access transfer. Normally, when data is transferred between memories or between an I/O device and memory, the data is transferred via the CPU, but DMA In the transfer, the DMAC controls the I/O bus to directly transfer data between memories or between an I/O device and memory. This invention applies to a case where DMA transfer is performed between an I/O device and a memory.

As shown in Figure 3, the I/O bus (5)
The devices (8a) to (8c) output a DRQ signal (DMA request signal) to the I/O bus, and
Input the ACK signal (DMA acknowledge signal). Also, the data human output signal, the l/OW signal which is the write strobe signal, and the 1/O signal which is the read strobe signal.
The R signal is connected to the I/O bus (5). Each I/O device has a dedicated channel for the DRQ signal and the DACK signal, and is assigned to channels 0 to n. In addition, each channel is given a priority by DMAC (6), where channel 0 has the highest priority, followed by channels 1, 2...n. shall be.

The case where the I/O device (8a) performs 1MA transfer will be described with reference to FIG. At point a, the I/O device (8
a) sets DRQO) to “H” and DMAC(6)
Makes a DMA transfer request to. DMAC(6) is I/
The DRQOH signal is input via the O bus (5), and this
When the MA request is accepted, the CPU (4) takes control of the I/O bus (5) and outputs the address to the memory (7) via the I/O bus (5) at time 5. At the same time, at time C, 0^CKOL is set to "L" to notify the I/O device (8a) that DRQO)l has been accepted. The I/O device (8a) connects to D via the I/O bus (5).
Input OL to AC, know that DRQOH has been accepted, and set DRQOH to “L” at time d.
AC (6) is memory (7) in case of memory read transfer.
On the other hand, in the case of memory write transfer, a read strobe signal is output to the I/O device at time e. In response to this read strobe signal, the memory (7) or I/
The O device outputs data to the I/O bus (5) at time f.

Next, at time 8, the DMAC (6) outputs a write strobe signal to the I/O device in the case of a memory read transfer, and to the memory (7) in the case of a memory write transfer. The memory (7) or I/O device (8a) inputs data on the I/O bus (5) at time n when the write strobe signal becomes H. Next, the DMAC (6) sets the DACKOL signal to "H" at time point i to notify the I/O device (8a) that one cycle of DMA transfer has ended. I/O device (8a
) sets the DRQOH signal to “H” at time i and starts the next DMA
A transfer request is issued, and data transfer is continued until the DMA transfer is completed, as in point a.

The I/O device (8a) has been explained above, but the I/O device (8a)
Devices (8b) and (8c) also perform DMA transfer using similar operations, except that the DMA channels are different.

Next, the priority order of DMA channels will be explained. In FIG. 5, at time k, the DMA0 channel, the request signal DRQO)l of the DMAI channel, and the DRQ
If IH is enabled at the same time, DMAC(6)
performs service for DRQOH with high priority and outputs DACKOL. Next, when the DMAC (6) reads the request signal of the DMAI channel at time i, which is T after the end of two cycles of DMA transfer on the DMA0 channel, DRQOH is set to "L" by OL to the DAC.
Since only DRQIH is "H", DMAC (6) provides service for DRQI)1.

However, as shown in Figure 6, the DMA transfer rate of the O channel is fast, and when the DMAC (6) reads the request signal at time i, which has passed beyond the time when the DMA0 channel has transferred the DMA, the DRQOH has already reached the next level. If a transfer request is issued and the level is 'H', DRQOH and DRQII (
is simultaneously high, so DMAC (6) provides service for DRQOH, which has a high priority.
As a result, one channel's DMA transfer is performed using the O channel's D
No calls will be accepted until all MA transfers are completed.

[Problem to be solved by the invention]

Since the conventional DMA device is configured as described above,
If the transfer rate of the high priority DMA channel is fast,
A DMA channel with a lower priority than that DMA channel cannot be accepted until all DMA transfers with a higher priority have been completed, so data transfer is not performed, and a DMA channel with a lower priority can be accepted. In order to
There were problems such as the need to reduce the transfer speed of DMA, which has a high priority.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a DMA device that does not interfere with the operation of lower-order DMA channels and does not require reducing the DMA transfer speed. shall be.

[Means to solve the problem]

A DMA transfer device according to the present invention includes a memory, a plurality of I/O devices having data transfer priorities, and a DMAC that controls data transfer between the memory and each I/O device.
to the I/O bus to connect multiple DMAs with priority
configuring the channel, each of the above 1/O devices has its own DMA
A data request signal is manually transmitted from a low-level DMA channel with a lower priority than the channel, and if the data request signal of the lower-level DMA channel is enabled at the time when its own data request signal is disabled, the next data is transferred based on the data request signal. The device is equipped with a gate signal output means for outputting a gate signal for suppressing the data request signal of the own DMA channel output in a cycle, and a gate circuit for suppressing the data request signal of the own DMA channel when outputting the gate signal. .

[Effect]

The DMA device according to the present invention gates the DRQ of its own DMA channel by the DRQ from the lower DMA channel, so that when the DRQ of the lower DMA requires service, the DMA device of the present invention gates the DRQ of its own DMA channel until the DRQ of the lower DMA is accepted. Since the next DRQ is not output, the DRQ of the lower DMA
It does not impede the operation of the device and does not significantly reduce its own DMA transfer speed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is DRQI here, but the DRQ of the DMA lower than the own DMA channel is connected to the data input and reset input, the inverted signal of the own DRQ is used as the T input, and the gate signal is output. (2) is an AND gate that inputs the gate signal of flip-flop (1) and gates its own DRQ, (3) is an inverter for inverting DRQ, and (8a) is an I/O device. It is.

Next, the operation will be explained with reference to the timing chart shown in FIG.

Assume that at time a, its own DRQH, lower-order DROH, and lower-order DRQIH are enabled.

At this point, the gate output of flip-flop (1) is “H”
”, the AND gate (2) does not inhibit DRQH and outputs it as DRQI). , performs service for DRQOH.As DACKOL becomes "L", DRQ) becomes "L" at time C, and at the same time, DRQOH also becomes "L".
” At this time, if the data output of the flip-flop (1), that is, DRQI)l is “H”, DRQH
becomes “L”, so that T of flip-flop (1)
A trigger signal is input to the terminal through an inverter (3), takes in DRQI), and sets the gate output to "L". Next, at time d, in order to perform the next DMA transfer, DR
Q) Let l be “H”, but at this point 1. Since the flip-flop (1) is inputting DRQIH, the gate output becomes L'', and the AND gate (2) is inputting, so it suppresses DRQH, and DRQOH is not output. 0 Next DMAC is at time e Attach DRQIH and set 0^CKIL to 11 LI'' at time e. DRQI
H is DRQ due to DACKIL becoming “L”
Since IH has been accepted, it becomes "L" at one point in time. Since the flip-flop (1) inputs DRQIH to the reset terminal, when DRQIH becomes "L", the gate output becomes "H". Therefore, AND gate (2) stops suppressing DRQH and outputs DRQOI (.

Although not shown in the chart of Figure 2, when DRQIH is not output, the flip-flop (1)
Since no gate signal is output, DRQII is output as is as DRQO)l.

In the above embodiment, the own DRQ is set to Och, and the lower DRQ is set to lch, but any channel from 0 to n may be used, and the lower DRQ is shown in which only one channel is input. , a plurality of lower-order DRQ channels may be logically summed and input.

(Effects of the Invention) As described above, according to the present invention, since the DRQ of the lower DM^ is input and the own DRQ is gated, the own DRQ transfer rate can be reduced as much as possible. Moreover, it is possible to obtain a DMA device that does not interfere with the OM^ transfer of the lower DMA.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a DMA device according to an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of the embodiment of FIG. 1, FIG. 3 is a block diagram showing a DM^ channel, and FIG. 5 and 6 are timing charts explaining the operation of the conventional OM^ channel. In the figure, (1) is a flip-flop, (2) is an AND gate, (3) is an inverter, (4) is a CPU, (5) is a
) is an I/O bus, (6) is a DMAC, (7) is a memory, and (8a) to (8c) are I/O devices. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] Multiple I/Os with memory and data transfer priorities
Together with the O device, a DMAC that controls data transfer between the memory and each I/O device is connected to the I/O bus to configure a plurality of DMA channels with priorities, and each of the I/O
The device inputs a data request signal from a low-level DMA channel with a lower priority than its own DMA channel, and when its own data request signal is disabled,
gate signal output means for outputting a gate signal for suppressing the data request signal of the own DMA channel to be output in the next data transfer cycle based on the data request signal if the data request signal of the lower DMA channel is enabled; A direct memory access device comprising: a gate circuit that suppresses a data request signal of its own DMA channel when outputting a signal.