JPS5990132A - Memory bank switching system of microcomputer system - Google Patents

Abstract

PURPOSE:To transfer data with high efficiency with no intervention of an I/O by setting a bank address in a DMA transfer mode in response to the present channel of a DMA controller. CONSTITUTION:A DMA controller 1 has plural DMA cycle counters (4 channels in the diagram), and these channels have their own priorities. Thus plural channels never work at a time. The DMA answer signals DACK0-3 of each channel are sent to an encoder 8 to detect an active channel. The data on the detected channel is delivered as a bank address, and at the same time a signal EO is sent to a latch 6' to inhibit the latch output. Then the mode is switched to the bank address setting by the DMA transfer from the bank address setting by a CPU. Thus it is possible to set a bank address in a DMA transfer mode with no intervention of an I/O to improve the data transfer efficiency to an external storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory bank switching method for a microcomputer system.

FIG. 1 shows a connection diagram of main parts of a microcomputer system using a conventional D81A controller (8257 manufactured by Ishitel Corporation). In this circuit DMAI
Controller t1) is normally in a state of waiting for a DMA request,
DMA request signal (DRQ) from either channel
If so, the DMA controller +1) enters a predetermined state SO and issues a hold request signal (
HRQ). CPUf21 DMA:lnt O-
Return to la 10. The DMA controller (1+ stays in the above state until a hold response is received, and then enters state S. It determines whether the DMA request is continuing or not every time it returns, and also sequentially changes the priority of the channel. Hold response signal (H
OLDA), a DMA cycle will be entered. Then, the DMA controller (1) outputs an address enable (i % (AE N)), enters the start of the DMA cycle, and acquires ownership of the bus.

Then, the lower eight bits of the address are output to the address buses An to A7, and the data bus l). , -D7, latches it with latch (4), and uses the latch output to output the upper eight addresses to 2 address buses A8 to AI6. It sends and receives data between the main memory (6) consisting of the main memory (6) and I10. Note that a strobe signal (ADR5TB) for latching the memory address of the upper eight pits by the latch (4) is also output to the latch (4). And IJAM controller (4) fdDMA response signal (D
ACK) corresponding to the corresponding channel, and moves to the next state. Note that (3) is a control bus, and through this control bus, memory write signals (MEMW) and memory read signals (
MEMR), 110 write signal (l10W), I10 read signal (110R), chip select signal CS, r0
A signal such as CLK is sent.

By the way, when the main memory (5) consists of multiple memory banks, a circuit like the one shown in Figure 2 is added and the CPU (
A bank address accessed by () and a bank address accessed by DMA controller D-(1) are provided, and a hold response signal (,) (O
When LDA) is set up, the latch for DMA transfer (6)
The bank address is latched to the CPU (small - from 2+).
When there is no lock response signal, a method has been used in which the CPU latch (7) latches all the lid bank addresses. However, with this method, it was not possible to switch the bank address for each P channel corresponding to Ilo connected to IJMA controller [1-La+0.

The present invention has been made in view of the above-mentioned problems, and its purpose is to change the bank address during DMA transfer to
To provide a memory bank switching method for a microcomputer system that can be set for each channel for MA transfer.

The present invention will be explained below with reference to Examples. FIG. 3 shows a circuit block diagram of an embodiment of the present invention. In this embodiment, the DMA controller (1) has four channels of DMAtj cycle counters, and each channel has a priority order and simultaneously performs DMA transfer. A general-purpose DMA controller such as the Intel 8257 is configured so that multiple channels do not work at the same time even if there is a request for the DMA response signal (DACKo) of each channel. Encoder (DACK,) (8)
By detecting that the DMA response terminal of any channel has become active, the encoder (8) detects which channel has entered DΔ4A transfer, and outputs the detected channel data as a bank address. Indicates that there was an input at the same time as the = sign (
go) is output to latch (6)'. This latch (6Y
is used to latch the bank address for the CPU, and when the signal EO is input to the terminal ('D E), the latch output is inhibited and the bank address is set by the CPU.
It is designed to switch to bank address setting using DMA transfer. Latch (4 is the latch of the conventional example in Figure 1 (4)
), it is used to latch the data at the upper address. In FIG. 3, AEN indicates an address enable signal output terminal, and ADSTB indicates an address strobe signal output terminal.

However, under normal conditions, the data bus D is controlled by the Ilo, :] control signal. -D, the bank address sent through is latched, and bank switching is performed under the control of cPUto. At the time of DMA transfer, the bank is switched to the main memo of the bank address corresponding to the channel where the D Ni A request was made.
Data is sent and received between the main memory (5) and the I10 corresponding to the channel under the control of the DMA controller (1).

The present invention provides a metric hunk that corresponds to each channel of the DMA controller. Input the DMA response signal to each channel that is set in advance and output from the DMA controller, detect the channel that is currently undergoing DMA transfer with the encoder, and output the bank address data of the channel multiple times to the encoder. Therefore, the bank address at the time of DMA transfer can be set to correspond to the current channel of the DMA controller. Therefore, the bank address at the time of DMA transfer can be set without passing through Ilo, and multi-user operation is possible. 'C is useful for data transfer with an external storage device in a data system in which a bank is assigned to each unit.

[Brief explanation of drawings]

Fig. 1 is an overall diagram of a conventional microphone D computer system, Fig. 2 is a block diagram of the main circuit used for replacing the tS sink, and Fig. 3 is a block diagram of the main circuit of an embodiment of the present invention. In the figure, m is the DMA controller, (2) is the CPU, (5) is the main memory, (8) is the rainbow coater, (L
IACK) is a DMA response signal. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] (1) In a microcomputer system that is equipped with a main memory consisting of multiple banks and that uses a DMA controller to perform DMA transfer between the main memory and the
A memory bank corresponding to each channel of the DMA controller is set in advance, and the DMA response signal to each channel output from the DMA controller is inputted, and the corresponding channel that is currently undergoing DMA transfer is detected by the encoder. A memory bank switching method for a microcomputer system, characterized in that bank address data of the channel is output from an encoder.