JPH03210816A - Mos semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the rising time and the falling time of an output signal by providing a series connection of a CMOS inverter composed of P/N-channel MOS transistors(TRs) and two MOS TRs and a capacitor connecting the inverter output and a common connecting point of the series connection and using the connecting point as an output terminal. CONSTITUTION:When a voltage Vcc is applied to an input terminal I as shown in a voltage waveform 2 at an input terminal, N-channel MOS TRs N1, N2 are turned on. Then the sum of currents flowing to the TRs N1, N2 from a level A through a load resistor RL toward GND is supplied and a voltage drop is caused across the resistor. In this case, a P-channel MOS TR P2 limits an output terminal voltage not to be below the voltage Vcc. When a level 0V is fed to the input terminal I, the TRs N1, N2 are turned off and the TR TRs P1 is turned on. Then as soon as the output of the CMOS inverter composed of the TRs P1, N1 goes to a level Vcc, the level at the output terminal O is the same as the level A. Thus, the input signal is converted into an output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS semiconductor integrated circuit, and more particularly to a MOS semiconductor integrated circuit having an output buffer circuit of a logic circuit.

[Conventional technology]

Conventionally, the output buffer circuit of a logic circuit built into this type of MOS semiconductor integrated circuit has an input terminal IN, an output terminal OUT, and diodes D and N, as shown in FIG.
It was composed of channel/channel MO8 transistor N, a potential person and ■ccI%11, a load resistance RL and a load capacitance C.
A series body with L is considered, and the common connection point is the output terminal O.
UT is connected.

FIG. 4 is a voltage waveform diagram illustrating the operation of the output balance circuit of FIG. 3. In FIGS. 3 and 4, when one input terminal INK voltage is applied as shown in the input terminal voltage waveform 6, in the input VCC section 8, since the N-channel transistor N is in the on state, the load resistor RL is applied from the potential A. A current flows in the GND direction and a voltage drop occurs, but it is limited by the diode D, and the voltage at the output terminal OUT becomes VCC as shown in the output terminal voltage waveform 5. In addition, in the input O section 7, since the transistor N is in the off state, the voltage OUT rises while being charged to the load valley 1tcL by the resistor RL, so the rise time is as shown in the output terminal voltage waveform 5. Has T.

This output terminal OUT was used as an output signal of the output buffer circuit.

[Problem to be solved by the invention]

The output buffer γ circuit of the conventional logic circuit described above has a drawback that the rise time Tr of the output signal is long and high-speed signal transmission cannot be performed. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS semiconductor integrated circuit in which the above-mentioned drawbacks are overcome, the rise time of an output signal is reduced, and high-speed signal transmission can be performed.

[Means to solve all problems]

The configuration of the MOS semiconductor integrated circuit of the present invention includes an 0MO8 inverter consisting of P and N channel MOS transistors whose gates are connected to input terminals, a MOS transistor whose gate input is the 6iJ input terminal, and an output voltage below a predetermined value. A series body with MO8I- and t diagonal metals is provided to limit the output from the CMOS inverter, and a capacitor connects the output of the CMOS inverter to a common connection point of the series body, and the connection point is used as an output terminal. Features.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a MOS semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, this embodiment has an input terminal I
N-channel M whose gate is driven by an input signal from
OS) An open drain output circuit using a transistor N, its output terminal 0, and a P channel MOS transistor Ps which limits the output terminal voltage so that it does not go below VCC, is gate driven by an input signal from the input terminal. It is configured to include a CMOS inverter including a P-channel MO8 transistor PI and an N-channel MOS transistor N1, and a capacitor C connected between the inverter output and the output terminal 0.

Next, the operation of this embodiment will be explained.

FIG. 2 is a voltage waveform diagram illustrating the operation of the embodiment shown in FIG. 1. In FIGS. 1 and 2, as shown in input terminal voltage waveform 2, when VCC is applied to the input terminal, the N-channel MOS transistor NI.

When Nx is in the on state, the potential A to G is applied to the load resistor Rx.
The sum of the currents flowing to the transistor Nt and the transistor Nx flows in the ND direction (however, the transistor N*Id
(The DC component above the capacitance C is cut off), and a voltage drop occurs. At this time, P channel MO8 transistor P
Since the output terminal voltage is limited by s so that it does not become less than vcc, the output terminal voltage waveform 1 of the input VCC section 4
It will be like KVcc.

Also, when input terminal IKOV is added, N-channel MO
S) Transistors Nt, Nst'i are in off state, P
Channel MO8 transistor P is turned on.

Then, since the capacitor C has been charged with the voltage vcc by then, the transistor P! and N.I.
At the same time that the output of the C'MO8 inverter based on K becomes VCC, VCC, which is twice the voltage of output terminal 0, is generated and becomes the same potential as A. This corresponds to the input 0■ section 3 of the output terminal voltage waveform l.

In this example, the explanation is given as [C≧l0XCL, A=2XVcc].

In this way, an input signal is converted into an output signal.

〔Effect of the invention〕

As explained above, the present invention includes a MOS transistor that operates according to an input signal from an input terminal, and a MOS transistor that limits the voltage at an output terminal so that it does not fall below a predetermined value (Vcc).
The S transistor, the capacitor connected to its output terminal, the MOS transistor, and the 0MO8 inverter using the MOS transistor have the effect of shortening the rise time and fall time of the output signal.

4,

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an MO8 semiconductor device circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a MO8 semiconductor device circuit according to an embodiment of the present invention. ! 3 is a circuit diagram of one output buffer circuit of a conventional logic circuit, and FIG. 4 is a voltage waveform diagram showing the operation of the output buffer circuit shown in FIG. 3. . 1.5...Output terminal voltage waveform, 2,6...
...Input terminal voltage waveform, 3, 7...Input Ov section, 4,8...Input VCC section, Tr...
...rise time, Pl, Ps...P channel M
O8 transistor, Nl p N'sN...-N channel MO8) Ranjisume, C... Capacitor, D... Diode sRL... Load resistance, CL... ...Load capacity, I, IN...
・Input terminal, 0, OUT...Output terminal.

Claims (1)

[Claims] P, N channel MOS with gate connected to input terminal
A CMOS inverter consisting of a transistor, a series body of a MOS transistor whose gate input is the input terminal, and a MOS transistor that limits the output voltage so that it does not fall below a predetermined value, and a common between the output of the CMOS inverter and the series body. 1. A MOS semiconductor integrated circuit, comprising: a capacitor for connecting a connection point; and the connection point serves as an output terminal.