JPH03211594A - Polarity detecting/fixing circuit for pulse signal - Google Patents

Abstract

PURPOSE:To make rapid detection that the polarity of an input pulse signal is inverted by providing a 1st ANDing means for ANDing the input pulse signal and a 2nd ANDing means for ANDing the output of a 2nd pulse signal generating means and the input pulse signal. CONSTITUTION:The input pulse signal A is inputted to the rising input side of a monostable multiplier circuit 1 and the falling input side of a monostable multiplier circuit 2 and is simultaneously respectively inputted to the one input side of an AND circuit 3 and a NAND circuit 4. The outputs of the AND circuit 3 and the NAND circuit 4 are inputted to a switch circuit 5, from which either one is selected and is inputted to a flip-flop circuit 6. An inversion signal is generated in synchronization with the rise of the input signal in the flip-flop circuit 6 and is outputted as a polarity inversion detection signal F. The polarity inversion of the input pulse signal A is detected from the resulted output signal F. The inversion of the polarity of the input pulse signal is detected at a high speed in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input synchronization/signal polarity reversal detection circuit and a polarity-travel circuit for multi-scan displays and the like.

[Conventional technology]

As described in Japanese Patent Application Laid-Open No. 57-4619, a conventional circuit derives a first level or second level signal depending on the polarity of an applied pulse signal, and uses exclusive logic between this signal and the pulse signal. By calculating the sum, it was possible to extract a pulse signal with a constant polarity regardless of the pulse signal applied.

[Problem to be solved by the invention]

The above conventional technology does not take into account the response time when the polarity of the input pulse signal is reversed, and when the polarity is reversed, the polarity of the pulse signal remains reversed until the first level or second level signal is derived. Therefore, there was a problem that the synchronization of images was disrupted.

An object of the present invention is to provide a circuit for quickly detecting that the polarity of an input pulse signal has been reversed.

Another object of the present invention is to quickly change the polarity of an input pulse signal.
Another object of the present invention is to provide a circuit for automatic stabilization.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a first monostable (or bistable) multicircuit and a second monostable (or bistable) multicircuit. logical product (or logical product negation) of two pulse signals generated from a multi-circuit (bistable) and the input pulse signal
A logical product (or logical product negation) circuit is provided to calculate the logical product (or logical product negation).
A first switch circuit for selecting one of the outputs of the circuit and a flip-flop circuit to which the signal selected by the first switch circuit is input are provided.

To achieve another object, the present invention further includes a second switch circuit for inverting the polarity of the input pulse circuit.

[Effect]

The first monostable (or bistable) multi-circuit outputs a pulse signal that occurs for a certain period of time from the rise of the input pulse signal, and the second monostable (or bistable) multi-circuit outputs a pulse signal that occurs for a certain period of time from the rise of the input pulse signal. In order to output pulse signals that occur for a certain period of time after the falling edge, an AND (or AND NOT) circuit outputs a constant level (or pulse) when the input pulse signal has negative polarity, and a pulse (or constant level) when the input pulse signal has positive polarity. level), and further, by inputting either one of these signals to a flip-flop circuit, it is possible to generate it Ht + it according to the polarity of the input pulse signal.
Outputs an “L” signal.

In addition, by using the "H" and 1 (L) signals as the switching signals of the first switch circuit, after the polarity of the input pulse signal is reversed,
Since a stable state is automatically set, there is no possibility of malfunction.

Further, by using the "H"1'L" signal as a switching signal for the second switch circuit, the polarity of the input pulse signal is forcibly inverted and outputted.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the accompanying drawings.

FIG. 1 shows an overall circuit diagram of this embodiment.

The input pulse signal A is input to the rising input side of the monostable multi-circuit 1 and the falling input side of the monostable multi-circuit 2, and is simultaneously input to the AND circuit 3.
．． and one input side of the logical AND NOT (NAND) circuit 4, respectively.

The monostable multi-circuit 1 detects the rising position of the input pulse signal A, and generates a constant pulse signal B (for example, half a cycle of the input pulse signal A) from this rising position.
Furthermore, the monostable multi-circuit 2 inputted to the other input side of the AND NOT circuit 4 detects the falling position of the input pulse signal A, and detects the falling position of the input pulse signal A by a certain width (for example, input pulse signal A). generate a pulse signal C with a half cycle of
It is input to the other input side of the AND circuit 3.

Next, the outputs of the AND circuit 3 and the AND NOT circuit 4 are respectively input to a switch circuit 5, and one of them is selected and input to a flip-flop circuit 6. In the flip-flop circuit 6, in synchronization with the rise of the input signal, if it is "H", it is 11 L, and if it is 'L', it is H.
'' is generated and output as a polarity reversal detection signal F. At the same time, this polarity reversal detection signal F is input as a control signal to the switch circuit 5 and switches the signal selection of the switch circuit 5.

On the other hand, the input pulse signal A is input to the input side of the NOT circuit 8 and one input side of the switch circuit 9 after being delayed for a certain period of time (several tens of nanoseconds) by the delay circuit 7 . Here, the delay circuit 7 has the function of correcting element delay. Further, the output of the NOT circuit 8 is input to the other input side of the switch circuit 9. Similar to the switch circuit 5, the switch circuit 9 receives the polarity reversal detection signal F as a control signal, switches the signal selection of the switch circuit 9 in synchronization with the switch circuit 5, and outputs the pulse selected by the switch circuit 9. Signal G is output.

Next, each signal operation will be explained in detail using FIGS. 2 and 3. FIG. 2 is a timing chart of each part when the input pulse signal A changes from negative polarity to positive polarity,
FIG. 3 shows a timing chart of each part when the input pulse signal A changes from positive polarity to negative polarity.

First, each signal operation when the input pulse signal A changes from negative polarity to positive polarity will be described below with reference to FIG.

When input pulse signal A is input with negative polarity, a signal is obtained by performing the logical product of signal B, which generates a negative pulse of a constant width from the rising edge of input pulse signal A, and input pulse signal A. is output as an "L" level signal and input to the flip-flop circuit 6. At this time, the signal F which is the output of the flip-flop circuit 6 is
11 L), and the negative polarity input pulse signal A is output as is as the output signal G. Next, when the input pulse signal A changes from negative polarity to positive polarity from time a in FIG. 1, a positive pulse signal is generated at the timing shown in FIG. At this time, the flip-flop circuit 6 changes the output signal F from the "L" level to the 11H# level in synchronization with the rising edge of the first pulse 5 of the signal. at the same time.

The signal selections of the switch circuit 5 and the switch circuit 9 are respectively switched to the other side, and the signal E is made the input signal of the flip-flop circuit 6, and the polarity inverted signal of the input pulse signal A is made the output signal G. At this time, since the signal E is held at the "L" level, the flip-flop circuit 6 is in a steady state.

As described above, it is possible to detect the polarity reversal of the input pulse signal A from the obtained output signal F, and even if the polarity of the input pulse signal A is reversed, the polarity is always constant (negative polarity in this example). A pulse signal G can be output.

Next, each signal operation when the input pulse signal A changes from positive polarity to negative polarity will be explained below using FIG.

When input pulse signal A is input with positive polarity, signal E is obtained by taking the theoretical product of input pulse signal A and signal C, which generates a positive pulse of a constant width from the falling edge of input pulse signal A. , #LP is output as a P+ level signal and input to the flip-flop circuit 6. At this time, the signal F which is the output of the flip-flop circuit 6 is I
IH" level, and the output signal G is a signal with the polarity inverted (negative polarity) of the input pulse signal A. 6 Next, at the point in the figure, the input pulse signal A has a positive polarity. When the polarity changes from negative to negative, a positive pulse signal is generated in the signal E at the timing shown in the figure. At this time, the flip-flop circuit 6 outputs the output signal F in synchronization with the rising edge of the first pulse of the signal E. "L'" from H11 level
Change the level. At the same time, switch the signal selection of the switch circuit 5 and the switch circuit 9 to the other side,
The signal A is used as the input signal of the flip-flop circuit 6, and the input pulse signal A is used as the output signal G as it is. At this time.

Since the signal R is held at the "L" level, the flip-flop circuit 6 is in a steady state.

As described above, the polarity reversal of the input pulse signal A can be detected from the output signal F obtained.

Even if the polarity of input pulse signal A is reversed, it will always have a constant polarity (
In this embodiment, a pulse signal G of negative polarity) can be output.

According to this embodiment, the polarity of the input pulse signal is automatically made constant, and the response when switching the polarity is fast (-
(within the cycle), which has the effect of reducing screen holes during switching. In addition, since polarity reversal of the input pulse signal can be detected at high speed (within - period),
Using this detection signal, it is possible to generate a signal for mode setting (for example, screen size setting, etc.) of a display, which is a single screen output device.

In addition, since it is possible to detect pulse signals whose polarity is reversed, it is possible to detect, for example, a cut pulse in the vertical retrace section of an NTSC signal, and it can also be applied to a detection signal generation circuit for each field. It is possible.

〔Effect of the invention〕

According to the present invention, it is possible to detect at high speed (within - period) that the polarity of the input pulse signal has been reversed.
By outputting this detection signal to the display device,
It can be used for mode settings such as screen size settings.

Furthermore, since the polarity of the input pulse signal is quickly and automatically made constant, there is almost no disturbance in the display screen during switching.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the polarity reversal detection circuit of the present invention, FIG. 2 is a timing chart of FIG. 1, and FIG.
3 is a timing chart of the figure. 1.2... Monostable multi-circuit, 3... Logical product (AND) circuit, 4... Logical product negation (NAND) circuit. 5.9...Switch circuit, 6...Flip-flop circuit, 7...Delay circuit, 8...NOT circuit. ■ Figure (α)

Claims (1)

[Claims] 1. In a pulse signal polarity detection/constant circuit having a signal input section to which an input pulse signal of positive polarity or negative polarity is applied, detecting the rising edge of the input pulse signal and detecting the rising edge of the input pulse signal and detecting the rising edge of the input pulse signal. A first pulse signal generating means for generating a pulse signal, and a second pulse signal generating means for detecting a falling edge of the input pulse signal and generating a pulse signal of a constant width are provided, and the first pulse signal a first logical product means for logically multiplying the output of the generating means and the input pulse signal; and a second logical product means for logically multiplying the output of the second pulse signal generating means and the input pulse signal. 1. A pulse signal polarity detection/constantization circuit, characterized in that it is provided with an AND means. 2. In claim 1, a first selection means for selecting either the output of the first logical product means or the output of the second logical product means; “H” or “, corresponding to the leading edge of the selected signal.
A pulse signal polarity detection/constant circuit, which includes level holding means for alternately holding and outputting an L" level, and uses the output of the level holding means as a selection control signal for the first selection means. 3. Claim 2. , a polarity inverting means for inverting the polarity of the input pulse signal, a second selection for selecting one of the input pulse signal whose polarity has been inverted by the polarity inverting means, and the input pulse signal. 1. A pulse signal polarity detection/constant circuit, comprising means for detecting and stabilizing the polarity of a pulse signal, wherein the output of the level holding means is used as a selection control signal for the second selection means.