JPH03211623A - Information processor - Google Patents

Abstract

PURPOSE:To speed up the execution of a double write type instruction by adding comparatively simple circuits such as a decoder, a flip flop, a register and a control circuit. CONSTITUTION:The control circuit 122 inputs the outputs of the flip flops 100 and 102, a register update instruction detection signal given through a line 1201 and a double write type instruction detection signal given through a line 1202 and outputs a control signal controlling selectors 110-113 to lines 1221 and 1222 based on prescribed logic. When the instruction stored in a register 6 is the double write type instruction, the register update instruction detection signal and the double write type instruction, both of which are the outputs of the decoder 120, are '1' and the content of an R field in the register 6 is set in a register 101, and data on an address (R field +1) is set in a register 103. Thus, the execution of the double write type instruction is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention provides processing for holding the number of a register that has not been updated among the registers updated by an instruction preceding an instruction that simultaneously updates two registers under pipeline control. The present invention relates to an information processing device.

Prior Art An information processing device that employs a method that divides a series of processing steps into a plurality of consecutive phases and has a pipeline that individually and consecutively executes instructions corresponding to each of the divided phases is used. It is called a line control type information processing device.

Further, an instruction in which one instruction updates both registers is called a double write type instruction. In the pipeline control type information processing device described above, the instruction preceding this double write type instruction serves as a register group that holds the numbers of registers that have not yet been updated among the registers to be updated.
There is a group of registers waiting to be confirmed.

Conventionally, when a double write type instruction is executed in a pipeline control information processing device, only one register number is registered in the pending registration register group per machine cycle. For this reason, it takes two machine cycles when the pending registration register group attempts to register two register numbers, and as a result, the execution speed of this type of instruction is slow.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an information processing device that eliminates the above-mentioned drawbacks and enables high-speed execution of double-write type instructions.

Structure of the Invention According to the present invention, there is provided an information processing apparatus of pipeline control type, which includes update instruction detection means for detecting that a first instruction is a register update instruction, and update instruction detection means for detecting that a first instruction is a register update instruction; double write type instruction detection means for detecting that the instruction is a double write type instruction that updates both of the instructions, and a plurality of confirmation waiting registration registers that hold unupdated register numbers among the registers updated by the preceding instruction to the first instruction. means, registration possibility detection means for detecting the possibility of parallel registration of a plurality of register numbers in these confirmation waiting registration register means, detection of a double write type instruction by said double write type instruction detection means, and said registration possibility detection means. and control means for controlling the register number of the first instruction not to be registered until the possibility of parallel registration of a plurality of register numbers becomes possible when registration is detected as impossible. A processing device is obtained.

Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings.

A pipeline control type information processing apparatus, which is an embodiment of the present invention, is composed of four stages. In other words, the D stage decodes instructions and generates addresses, the address translation buffer (hereinafter referred to as TLB) converts the addresses generated in this D stage, the O stage indexes the cache memory and continuously outputs memory data, and the arithmetic circuit. It consists of an E stage which performs calculations on memory data given from the O stage, and a W stage which stores the calculation results of the E stage.

Referring to FIG. 1, one embodiment of the present invention includes a register 6 for holding instruction words in the D stage. The instruction word stored in this register 6 has the following five fields.

That is, the OP field that specifies the operation of the instruction, the R field that indicates the number of the register to be updated, the B field that indicates the number of the pace register used for address generation, the X field that indicates the number of the general-purpose register used for address generation, and the address. It has a D field indicating the displacement part used for generation.

In addition, the D stage includes pace register group 1 indexed by the number shown in the B field, general register group 2 indexed by the number shown in the X field, and these pace register group 1 and general register group 2. It includes an adder 10 that adds the output with the D field to generate an operand address.

The operand address generated by the adder 10 is stored in the register 3 and then given to TLBll. T
LBII converts a logical address into a physical address, and the 0 stage has this TLBII and this T
A cache memory 12 is provided that outputs data from a location indicated by an address converted by LBII.

After this data is stored in the register 4, it is output as calculation data. The E stage is equipped with an arithmetic circuit 13 that operates on given data. The calculation result is stored in register 5.

A control system according to an embodiment of the present invention is configured as follows.

The D stage inputs and decodes the OP code of the instruction stored in register 6, outputs a signal to line 1201 when the instruction is a register update instruction, and outputs a signal to line 1201 when the instruction is the above-mentioned double write type instruction. , a decoder 120 that outputs a signal to line 1202, and an adder 122 that adds 1 to the number of the register to be updated given from the R field of register 6.

In the 0 stage, a selector 112 selects either the register update instruction detection signal or the double write type instruction detection signal applied from the decoder 120 via lines 1201 and 1202, and a flip-flop stores the selection result of this selector 112. 102, a selector 11O1 that selects either the output from this flexible flop 102 and the register update instruction detection signal applied via line 120; a flip-flop 100 that stores the selection result of this selector 110; 102, the register update command detection signal given through line 1201 and the double write type command detection signal given through line 1202, and the outputs of lines 122 and 1222 are input based on FIGS. 4 and 5.
A control circuit 122 outputting a control signal to the control circuit 1
22 through the line 1222, the register number to be updated from the R field of register 6 and the adder 1 added by +1 to this register number.
A selector 113 that selects one from 2+, and a register 1 that stores the selection result from this selector 113.
03, the selector 111 selects which one of the output from the register 1.3 and the number of the register to be updated given via the line 61 is selected by the selection instruction signal given from the control circuit 122 via the line 1221; Register 10 that stores the selection results from .11
1.

The output of flip-flop loo is flip-flop 10
4, and then stored in the flip-flop ■o6. Further, the output of register lO1 is stored in register 105 and then in register 107.

The E stage includes an AND gate 123 that performs the logical product of the double write type instruction detection signal applied via the line 12o2 and the output of the flip-flop 102. The output of this AND gate 123 is output to line I231 to hold the instruction in register 6 and reset flip-flop 102. The values of the flip 7 C7 tabs 100, 102, 104 and JOB +7 indicate whether the values of registers 1 (11, 1 (13, 1) (15 and 107) are valid or not, respectively.

In this example, the flip-flops ioo,i.

2, 104 and 10B and registers 101.103
, 105 and 107 are referred to as a group of registration registers waiting for confirmation. These register groups operate in synchronization with the pipeline clock signal.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1 and FIG. 2A, the instruction A currently stored in register 6 at timing TI is a double write type instruction that registers the contents of the R field and the contents of the (R field + 1) address. do. At this time, it is assumed that there is no valid register number in the confirmation waiting registration register group. That is, flip-flops 100, 102, 104, 104 and 10B are all set to "o".

Line 120 which is the output of decoder 120! Both the upper register update instruction detection signal and the double write type instruction detection signal on line 12o2 are "1", and flip-flop 1
Both 00 and 102 are "0".

At timing 2, "1" is set in the flip-flop 100 and the contents of the R field of the register 6 are set in the register 101 according to the logic shown in FIG. Note that in FIGS. 2A, 2B, 3A, and 3B, R(A) indicates the number of the register updated by instruction A, and R(B) indicates the number of the register updated by instruction B. .

At this timing 2, #1'' is set in the flip-flop 102 and the register 103 is set according to the logic shown in FIG.
The data at address (RA+1) is set in .

When instruction B, which is a subsequent instruction of instruction A, is an instruction that updates one register, the register update instruction detection signal on line 1201 is "1" at timing T2, and the double write type instruction detection signal on line 1202 is "1". is “0”. According to the logic of FIG.
is set to the number given via line 1o31. Further, in accordance with the logic of FIG. 5, flip-flop 102 is set to 1'' applied via line 1o21, and register 103 is set to the contents of the R field of instruction B.

FIG. 2B shows the conventional operation of an instruction in which instruction A is a double write type instruction and instruction B updates only one register. A comparison between FIG. 2A and FIG. 2B shows that the present invention can be executed one machine cycle faster than the prior art.

Next, the operation when both instructions A and B are double write type instructions will be explained in detail. Referring to FIGS. 1 and 3A, the operation of instruction A is the same as the operation of instruction A described above.

Instruction B includes the contents of R field and (R field + 1
) is a double write type instruction that registers the contents of an address.

At timing T2, the flip-flop 102 is activated by instruction A.
is set to "1" and the double write type instruction detection signal on the line 1202 is "1", so the AND gate [23 is the line 123 [to “1′
Output.

As a result, at timing T3, according to the logic shown in FIG. 4, "1" is set to the flip-flop 100 through the line 1021, and "1" is applied to the register 101 through the line 031.

At timing T4, according to the logic of FIG.
is set, and the register number updated by instruction B is stored in register 101. Further, in accordance with the logic shown in FIG.
+1. ) address data is stored.

FIG. 3B shows the conventional operation in which both instructions A and B are double write type instructions.

Comparing FIG. 3A and FIG. 3B, it is clear that the present invention is better than the prior art even when double write type instructions are executed consecutively.
One machine cycle can always be executed quickly.

Effects of the Invention In the present invention, by adding relatively simple circuits such as a decoder 120, an adder 121, a flip-flop 102, a register 103, a control circuit 122, and an AND gate [23], it is possible to speed up the execution of a double write type instruction. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2A is a diagram showing an embodiment of the present invention.
Diagram 2B for explaining the operation when is a double write type instruction and instruction B is an instruction that updates only one register.
3A is a diagram showing the operation of the prior art for comparison with the operation in FIG. 2A, FIG. 3A is a diagram for explaining the operation when both instructions A and B are double write type instructions, and FIG.
This figure is a diagram for comparison with the operation of FIG. 3A, and FIGS. 4 and 5 are truth tables showing the operation of the control circuit 122. Explanation of symbols of main parts 1... Pace register group 2... General purpose register group 3, 4. 5. 6.101,103゜105.10
7...Register 1.0.121...Adder 11...TLB 12...Cache memory 13...Arithmetic circuit 100.102゜104, 106...Blip-flop 120.
... Decoder 122 ... Control circuit 123 ... AND gate

Claims (1)

[Claims] (1) A pipeline control type information processing device, which includes an update instruction detection means for detecting that a first instruction is a register update instruction, and a double write in which the first instruction updates both registers. double write type instruction detection means for detecting that the instruction is a type instruction; a plurality of waiting-for-determination registration register means for holding unupdated register numbers among the registers to be updated by the preceding instruction for the first instruction; Registration possibility detection means for detecting the possibility of parallel registration of a plurality of register numbers in the registration register means, detection of a double write type instruction by the double write type instruction detection means, and detection of registration impossibility by the registration possibility detection means and control means for controlling the register number of the first instruction not to be registered until the possibility of parallel registration of a plurality of register numbers becomes available.