JPH03139727A - Advanced controller - Google Patents

Abstract

PURPOSE:To improve the performance of advanced control by invalidating a detection signal indicating that effective information is held in all register groups which wait to be determined when detecting a following instruction being an instruction which does not update the contents of the registers. CONSTITUTION:When the following instruction is the instruction which does not update the register groups 5 and 6 and effective register numbers are held in registers 19 - 22 with a precedent instruction, 0 is set in an FF 15 by a decoder 14. At this time, an AND gate 24 outputs 1 as a determination wait signal and an AND gate 25 outputs 0. Therefore, even if effective register numbers are held in all the registers 20 - 22 in a register group which waits to be determined, no influence is exerted upon the synchronous control over pipeline processing if the instruction does not update the register groups 5 and 6, and the processing can be carried on. Consequently, the performance of the advanced controller can be improved.

Description

TECHNICAL FIELD The present invention relates to an advance control device, and more particularly to a advance control device for a pipeline type information processing device.

Conventional technology Conventionally, in this type of advance control device, even if the subsequent instruction does not update the register used for address generation, a fixed waiting system that holds the register number used at each stage of pipeline processing is used. When valid information is held in all registered register groups, processing of subsequent instructions is not started until the preceding instruction updates the registers and there is space in the pending registration register group.

That is, as shown in FIG. 3, an instruction that does not update a register [for example, RR (register L).

regisL, er) A valid register number is held in each register of the confirmation waiting registration register group by the instructions ■ to ■ preceding instruction 1■, and two machine cycles after the instruction ■ is set to the A stage. When the register is updated, the instruction ■ is processed through the A stage, 0 stage, E stage, and W stage two machine cycles later than the instruction ■ after the confirmation wait signal changes from 1# to “0”. I'm going to go there.

Here, the D stage is a stage for decoding an instruction word, and the A stage is a stage for reading a register used for address generation and performing address addition.

0 stage is TLB (translation
1ookasldebuffer) and the cache to read memory data, and the E stage is a stage for performing calculations using an arithmetic circuit.
The W stage is a stage that stores calculation results.

In such a conventional advance control device, even if the subsequent instruction does not update the register, the processing of the subsequent instruction is executed when valid information is held in all the registered registers waiting for confirmation. Since this is not performed, there is a drawback that the performance of advance control deteriorates.

OBJECTS OF THE INVENTION The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and an object of the present invention is to provide a advance control device that can improve the performance of advance control.

Structure of the Invention The advance control device according to the present invention detects that valid information is held in a group of pending registration registers each holding a register number of a register whose contents are to be updated, and in all of the group of registers waiting to be confirmed. and a first detecting means to wait for the processing of the subsequent instruction when the first detecting means detects that valid information is held in all of the confirmation waiting registration register group. The preceding control device is configured to perform control such that the subsequent instruction is an instruction that does not update the contents of the register; The present invention is characterized by further comprising means for invalidating the detection result of the first detection means when it is detected that the contents of the register are not updated.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the register is a register that holds an instruction word, its OP field specifies the operation of the instruction, the R field is the register number of the register to be updated, and the B field is the base register used for address generation. The X field indicates the register number of the general-purpose register used for address generation, and the D field indicates the displacement used for address generation.

Registers 2 to 4 each hold a base register number, a general-purpose register number, and a displacement I. used for address generation.

Register 1 (BR) 5 is a base register group, register group (GR) 6 is a general-purpose register group, and adder 7
The data used to generate memory operand addresses is held in the memory operand address. The memory operand address generated by the adder 7 is stored in the register 8.

Based on the output of register 8, TLB 9 and cache 1.0 are indexed, and memory data is read from cache 10 and stored in register 1.

The arithmetic circuit 12 performs an arithmetic operation on the memory data stored in the register 1 and stores the result of the arithmetic operation in the register 13.

The decoder 14 detects whether the instruction held in the register is an instruction to update the register group 5.6,
The detection result is a flip-flop (hereinafter referred to as FF) 1
It is stored in 5.

The output of FF15 is passed around by FF'16 to FF'18 in synchronization with each stage of pipeline processing.

Register 0 contains the register number updated by the A-stage instruction, register 20 contains the register number of the register updated by the O-stage instruction, register 21 contains the register number of the register updated by the E-stage instruction, and register 22 contains the register number of the register updated by the E-stage instruction.
holds the register numbers of the registers updated by the W stage instruction. These registers 19-22 are synchronized with pipeline processing.

Here, in one embodiment of the present invention, D, AO, E,
A pipeline process consisting of five stages of W is performed, and the D stage is a stage for decoding and reading the instruction word.
The A stage is the stage where the register used for address generation is read and the address is added to j-+, and the 0 stage is the TL stage.
The E stage is a stage in which memory data is read by indexing B9 and the cache 10, the E stage is a stage in which an arithmetic operation is performed using the arithmetic circuit 12, and the M stage is a stage in which the result of the arithmetic operation is stored.

The pipe synchronization circuit 23 generates control signals for the registers and the like of each of the above stages.

FIG. 2 is a diagram showing the operation of an embodiment of the present invention. The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

For example, if the following instruction ■ does not update register groups 5 and 6 (RR)
er) instruction, when valid register numbers are held in registers 19 to 22 by instructions ■ to ■ preceding this instruction ■When set to A stage, FF
15 is set to 0'' by the decoder 14.

At this time, the AND gate 24 outputs 1" as a confirmation wait signal.
However, the AND gate 25 outputs O'', so even if valid register numbers are held in all registers 20 to 22 of the register group waiting for confirmation, the instruction , 6 do not update, the synchronization control of pipeline processing is not affected and the subsequent processing can be continued.

In the conventional system, the confirmation wait signal from the AND gate 24 was used as it was for synchronization control of pipeline processing, so the instruction
, 6 is not updated, no processing is performed while valid information is held in all registers 20 to 22 of the pending registration register group.

Therefore, considering the instruction (2), it takes 7 machine cycles from the D stage to the W stage in the conventional system (see Figure 3), whereas in the embodiment of the present invention it takes 5 machine cycles from the D stage to the W stage. Only machine cycles are required (see Figure 2). In other words, in one embodiment of the present invention, the command
This means that the following processing can be performed.

This means that the slower the register group 5.6 is updated, the greater the difference in performance between the conventional system and the embodiment of the present invention becomes.

In this way, when the decoder 14 detects that the following instruction ■ is an instruction that does not update the register group 5.6, the confirmation wait signal from the Antogame 1 and 24 is invalidated in the Antogame 1 and 25. By doing so, when valid information is held in all registers 20 to 22 of the register group 5.
It is possible to quickly process the instruction (2) which does not perform any update in step 6.

Therefore, the performance of the advance control device can be improved.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when it is detected that a subsequent instruction is an instruction that does not update the contents of registers, it is detected that valid information is held in all registers waiting for confirmation. There is an effect that the performance of advance control can be improved by invalidating the detection signal shown.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of an embodiment of the present invention,
FIG. 3 is a time chart showing the operation of the conventional example. Explanation of symbols of main parts 1 to 4, 8. ], 1. . 13.19-22...Register 56...
Register 8V] 0 7... Adder 9... TLB 10... Cache] 2... Arithmetic circuit 14... Decoder 15-18. ...Flip-flop 23...
...Pipe synchronous circuit 24.25...And gate

Claims (1)

[Claims] (1) A group of registration registers waiting for confirmation, each holding the register number of the register whose contents are to be updated, and a first detection means for detecting that valid information is held in all of the group of registration waiting registration registers. and when the first detection means detects that valid information is held in all of the confirmation waiting registration register group, the preceding control device controls to wait for processing of a subsequent instruction. , a second detection means for detecting whether the subsequent instruction is an instruction that does not update the contents of the register; and the second detection means detects that the subsequent instruction does not update the contents of the register. and means for invalidating the detection result of the first detection means.