JPH03211655A - Multistage wait control central processing unit - Google Patents

Abstract

PURPOSE:To control a peripheral equipment whose speed is slow by inserting a wait into the inactive part of a write signal and a read signal. CONSTITUTION:When a control circuit 2 controls the writing and reading of data as against the peripheral equipment 6 through a bus interface circuit 4, it informs a wait control circuit 3 of the type of a bus cycle which is executed at present (type of peripheral equipment 6). When it comes to time for starting the wait, the wait control circuit 3 gives the instruction of holding to the control circuit 2 and copies the wait value of a wait register for active 31 or a wait register for inactive 32 corresponding to a wait counter 33 into the wait counter 33. The wait value of the wait counter 33 is subtracted one by one at every clock. When it comes to '0', the instruction of holding to the control circuit 2 is stopped. Thus, the peripheral equipment 6 composed of peripheral LSI whose speed is slow is controlled without providing a timing adjusting circuit for an external part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multistage weight control central processing unit, and more particularly to a central processing unit that performs weight control during data write control and read control of peripheral devices.

[Conventional technology]

In the conventional central processing unit, the peripheral LS that constitutes the peripheral device
In order to match the data processing speed of I, etc., weights were inserted only into the active parts of the write and read signals.

[Problem to be solved by the invention]

When writing data to the peripheral LSI mentioned above, there are those that take in the data when the write signal goes from active to inactive, and when reading and outputting data, when the read signal becomes active, data output starts and the input takes place. Some stop data output when activated.

This type of peripheral LS developed for low-speed central processing units
When controlling I using a high-speed central processing unit, for example, when writing data from the central processing unit to a peripheral LSI, the peripheral LSI needs to hold the data after the write signal becomes inactive. In some cases, the write operation may not be able to be performed normally. Also,
On the other hand, when the central processing unit reads data from the peripheral LSI, the time from when the read signal becomes inactive until the data output of the peripheral LSI stops is long, and the central processing unit cannot wait until the next bus cycle. It may interfere with processing.

In these cases, it is necessary to re-develop a peripheral LSI for the high-speed central processing unit, or to install a circuit that holds write data, a circuit that stops the bus cycle, or a write signal between the central processing unit and the peripheral LSI. This method has two disadvantages: (1) it is necessary to provide a circuit for creating a signal that accelerates the inactivity of the read signal;

SUMMARY OF THE INVENTION An object of the present invention is to provide a device weight control central processing unit comprised of slow peripheral LSIs without providing an external timing adjustment circuit.

[Means to solve the problem]

The multi-stage wait control central processing unit of the present invention is a central processing unit that performs weight M control during write control and read control of data in a peripheral device. a first weight value storage means for storing a weight value corresponding to the inactive portion of the write signal and the read signal; a second weight value storage means for storing a weight value corresponding to the wait time for the inactive portion of the write signal and the read signal; 1st and 2nd
and weight control means for inserting time weights corresponding to each of the weight values stored in the weight value storage means into the active portion and the inactive portion of the write signal and the read signal, respectively.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The multi-stage weight control central processing unit 1 of this embodiment includes a control circuit 2 that controls the entire system, a weight control circuit 3 that controls the weight of the control circuit 2, and input/output devices and memory devices configured with peripheral LSIs. It includes a peripheral device 6 and a bus interface circuit 4 connected via a bus router.

The wait control circuit 3 includes an active wait register 31 that stores a weight value (the number of clocks to wait) for each type of peripheral device 6 (peripheral LSI) for the active portion of the write signal and read signal, and an active wait register 31 that stores the wait value (number of clocks to wait) for the active portion of the write signal and read signal. Inactive weight register 32 that stores weight values for each type of peripheral device 6 for the part
and a weight counter 33 for subtracting and counting the weight value.The operation will be explained next.

The control circuit 2 sets the wait value (number of taroks) corresponding to the required wait time for each type of peripheral device 6 in the active wait register 31 and inactive wait register 32 of the wait control circuit 3 in advance.
Store it.

The control circuit 2 controls data writing to the peripheral bag W6 via the bus interface circuit 4. When performing read control, the wait control circuit 3 is notified of the type of bus cycle currently being performed (type of peripheral device 6). The wait control circuit 3 controls the control circuit 2 at the time to start the wait.
A hold instruction is issued to the wait counter 33, and the weight value of the active weight register 31 or the inactive weight register 32 corresponding to the wait counter 33 is written to the wait counter 33. Then, the weight value of the weight counter 33 is decremented by "1" every clock, and "0" is obtained.
When this happens, the hold instruction to control circuit 2 is stopped. The control circuit 2 temporarily suspends processing while the hold instruction is issued.

Figure 2 shows the light signal. FIG. 7 is a diagram illustrating an example of timing when a wait is inserted after a read signal becomes inactive.

The operation timing of each part signal during write control will be explained according to Fig. 2. An address signal (T1) specifying the peripheral device 6, an address latch enable signal (T2), and a signal τ are outputted from the bus interface circuit 4 of the multi-stage wait control central processing unit 1 onto the bus controller, and the data is output with a delay of 170 times (TO). (T3) and a write signal (T4) are output. When writing to the peripheral LSI of the specified peripheral device 6, the input data is held from when the write signal (T4) becomes inactive (time tO) until time L2, as shown by T5. 1) Necessary force (Yes, if you do not insert a weight here, the time tl & this data (T3)
(disappears), and normal writing power is no longer possible. Therefore, if 170 waits before time tl are inserted, the data (T3) force is extended until time t3, allowing normal writing to the peripheral LSI.

Next, the operation timing of each part signal during read I control will be explained with reference to FIG. 2 in the same manner as above. An address signal (T1) specifying the peripheral device 6 and an address signal enable signal (T2) are output from the interface circuit 4 of the multi-stage wait control central processing unit 1 to the bus controller. A read signal (indicated by <74, which is the same as the above write signal) is output with a delay of TO.When reading from the peripheral LSI of the specified peripheral device 6, the read signal (T4) becomes active. It outputs data (indicated by <T5, which is the same as the input data above), becomes inactive (time tO), and then stops outputting (time t2).Here, if a wait is not inserted, the next bus cycle starts from time L1 and peripheral LSI data (T5
) interferes with the operation of that bus cycle. Therefore, if a wait is inserted for one clock before time L1, the start of the next bus cycle is extended to time 3, so normal operation can be performed without being disturbed by data (T5).

〔Effect of the invention〕

As explained above, the present invention enables a device constructed from slow peripheral LSIs without providing an external timing adjustment circuit by inserting weights into the inactive portions of write signals and read signals. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the timing when a wait is inserted after the write signal and read signal become inactive. DESCRIPTION OF SYMBOLS 1... Multistage weight control central processing unit, 2... Control circuit, 3... Wait control circuit, 4... Bus interface circuit, 5... Bus, 6... Peripheral device, 31...・Active weight register, 32...
Inactive wait register, 33...wait counter.

Claims (1)

[Claims] In a central processing unit that performs wait control during write control and read control of data in a peripheral device, a first weight that stores a wait value corresponding to a wait time for an active portion of a write signal and a read signal to the peripheral device. a value storage means, a second weight value storage means for storing a weight value corresponding to a wait time for an inactive portion of the write signal and the read signal, and a weight value stored in the first and second weight value storage means. a multi-stage weight control central processing unit, comprising weight control means for inserting time weights corresponding to respective weight values into active and inactive parts of the write signal and the read signal, respectively. .