JPH03211838A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03211838A JPH03211838A JP746190A JP746190A JPH03211838A JP H03211838 A JPH03211838 A JP H03211838A JP 746190 A JP746190 A JP 746190A JP 746190 A JP746190 A JP 746190A JP H03211838 A JPH03211838 A JP H03211838A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- pads
- bonding
- compression
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 14
- 238000005520 cutting process Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 12
- 239000011521 glass Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000002788 crimping Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、フィルムやガラス等の実装基板上に形成され
た電極と半導体装置側の電極とを圧着接着させる工法を
用いて、実装される半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device that is mounted using a method of pressure-bonding an electrode formed on a mounting substrate such as a film or glass to an electrode on the semiconductor device side. It is related to.
従来の技術
電子回路の高密度実装化に伴ない、半導体装置側の電極
を、ガラス基板上に形成された電極と接着するＣＯＧ
（チップオングラス）工法およびフィルム上の電極と接
着するＴＡＢ（テープオートメイテッドホンティング）
工法等の実装技術が、今日用いられている。Conventional technology With the trend toward higher density packaging of electronic circuits, COG, which adheres electrodes on the semiconductor device side to electrodes formed on a glass substrate,
(Chip-on-glass) method and TAB (Tape Automated Honting) that adheres to the electrode on the film
Mounting techniques such as construction methods are used today.
第２図は、前記実装の工法に用いられる半導体装置の上
面図を示したものである。■は、半導体装置をチップに
切り分けるための切削領域、２は電子回路の作り込まれ
た能動領域、３．４は半導体装置の外部回路と接続され
るパッドであり、このうちパッド４は偏在して配置され
たパッドの１つである。FIG. 2 shows a top view of a semiconductor device used in the mounting method described above. 2 is a cutting area for cutting the semiconductor device into chips, 2 is an active area where electronic circuits are built, and 3.4 is a pad connected to the external circuit of the semiconductor device. Of these, pad 4 is unevenly distributed. This is one of the pads placed in the area.
第３図は、前記ＣＯＧ工法により半導体装置を実装した
時の接着部分の断面図である。１０はガラス基板、１１
はガラス基板１０上にもうけられた電極、１２は半導体
装置基板、１３は半導体装置基板１２上の配線金属層、
１４は半導体装面基板１２上の絶縁保護膜、１５は配線
金属層１３゜絶縁保護膜１４で構成されたパッド上に形
成された突起電極である。FIG. 3 is a sectional view of a bonded portion when a semiconductor device is mounted using the COG method. 10 is a glass substrate, 11
12 is an electrode provided on the glass substrate 10, 12 is a semiconductor device substrate, 13 is a wiring metal layer on the semiconductor device substrate 12,
Reference numeral 14 represents an insulating protective film on the semiconductor substrate 12, and 15 represents a protruding electrode formed on a pad composed of the wiring metal layer 13° and the insulating protective film 14.
電極１１と突起電極１５との間に導電性接着剤１６を用
い、ガラス基板ＩＯと半導体装置基板１２を圧着するこ
とにより実装される。このため圧着こより各端子ごとに
、印加される荷重の大きさにより接着強度、抵抗値等の
パラメータが変化する。ＴＡＢ工法も同様である。した
がって、第２図に示すパッド配置の半導体装置を前記工
法により実装した場合、圧着時の印加荷重は、−様に配
置され、パッド数の多い側にあるパッド３より、偏在し
、かつパッド数の少ない側にあるパッド４の方が大きく
なる。The semiconductor device substrate 12 is mounted by using a conductive adhesive 16 between the electrode 11 and the protruding electrode 15 and pressing the glass substrate IO and the semiconductor device substrate 12 together. For this reason, parameters such as adhesive strength and resistance value vary depending on the magnitude of the load applied to each terminal of the crimped wire. The same applies to the TAB method. Therefore, when a semiconductor device with the pad arrangement shown in FIG. The pad 4 on the side with less is larger.
発明が解決しようとする課題
半導体装置を前記圧着工法により実装した場合、パッド
の数２間隔、装置によっては接着強度や抵抗等のパラメ
ータの端子間偏差が大きくなり、信頼性に問題が生じる
。最悪の場合、荷重の加わり方によっては、接着のｊ？
ｌＩ ｍを生じる等、製造歩留りを下げるという問題が
あった。Problems to be Solved by the Invention When a semiconductor device is mounted using the above-mentioned crimping method, deviations between terminals in parameters such as adhesive strength and resistance become large depending on the spacing between pads and the device, resulting in problems in reliability. In the worst case, depending on how the load is applied, the adhesion j?
There is a problem in that the production yield is lowered, such as the production of lIm.
本発明は上：［ｌ！、従来の問題点を解決するもので、
圧着工法による前記パラメータの端子間偏差を小さ（し
、信頼性および歩留りを向上することのできる半導体装
置を提供することを目的とする。The present invention is described above: [l! , which solves the conventional problems,
It is an object of the present invention to provide a semiconductor device that can reduce the deviation between terminals of the parameters due to the crimping method and improve reliability and yield.
課題を解決するための手段
この目的を達成するために本発明の半導体装置は、外部
回路との接続に供されるパッドの他、接続には供されな
いパッドを有する構成をもつ。Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention has a structure that includes pads that are not used for connection in addition to pads that are used for connection to an external circuit.
作用
この構成により、半導体装置のパッド配置の偏在を避け
、−様な配置とすることにより、圧着工法における印加
荷重等の物理的要因の平均化を図ることができ、接着強
度、抵抗値等のパラメータの端子間偏差を小さくし、工
程を安定化して、信頼性や歩留りを向上させることがで
きる。Function: With this configuration, it is possible to avoid uneven distribution of pads on semiconductor devices, and by arranging them in a negative manner, physical factors such as applied load in the crimping method can be averaged, and adhesive strength, resistance value, etc. It is possible to reduce the deviation of parameters between terminals, stabilize the process, and improve reliability and yield.
実施例
以下、本発明の一実施例につき、図面を参照しながら説
明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例における半導体装置の上面図
を示すものである。第１図において、１は切削領域、２
は能動領域、３，４は半導体装置の外部回路と接続され
るパッドで、これらは従来例の構成と同じである。２０
は従来例の構成に追加して配置された外部回路とは接続
されない疑似的なパッド（以下ダミーパッドという）で
ある。FIG. 1 shows a top view of a semiconductor device in one embodiment of the present invention. In Fig. 1, 1 is the cutting area, 2
3 is an active region, and 3 and 4 are pads connected to an external circuit of the semiconductor device, which have the same structure as the conventional example. 20
is a pseudo pad (hereinafter referred to as a dummy pad) which is placed in addition to the conventional configuration and is not connected to an external circuit.
ダミーパッド２０は、少なくとも１組の対辺の、おのお
のの近傍に、半導体装置のパッド配置を偏在させること
なく−様になるよう配置されている。The dummy pads 20 are arranged in the vicinity of at least one set of opposite sides so that the pads of the semiconductor device are not unevenly distributed but are arranged in the same manner.
この結果、上記構成の本実施例は、実装基板との圧着時
において、ダミーパッド２０をもうけたことによる−様
なパッド配置により、印加荷重が分散し、各端子へ平均
化される。したがって圧着工法における一部端子での接
着の剥離等の問題が解消し、前記パラメータの端子間偏
差が小さくなるから、製造歩留り、信頼性ともに向上す
る。As a result, in this embodiment having the above-mentioned configuration, when the terminal is crimped with the mounting board, the applied load is distributed and averaged to each terminal due to the dummy pad 20 and the pad arrangement. Therefore, problems such as peeling of adhesive at some terminals in the crimping method are solved, and deviations in the parameters between terminals are reduced, so that both manufacturing yield and reliability are improved.
なお、上記実施例では、パッド配置を「偏在することな
（−様に」と表現したが、例えば、すべてのパッドを半
導体装置の二軸に対し対称に、等間隔に配置すれば前述
した効果が最大となる。In the above embodiment, the pad arrangement was expressed as "not unevenly distributed", but for example, if all the pads are arranged symmetrically with respect to the two axes of the semiconductor device and at equal intervals, the above-mentioned effect can be obtained. is the maximum.
発明の効果
本発明は、半導体装置のパッドに、外部回路との接続に
供する目的以外のダミーパッドを追加することにより、
実装基板上に半導体装置を圧着する工程で、歩留り及び
信頼性を向上させることのできる優れた半導体装置を実
現できるものである。Effects of the Invention The present invention adds dummy pads for purposes other than connection with an external circuit to the pads of a semiconductor device.
In the process of press-bonding a semiconductor device onto a mounting board, it is possible to realize an excellent semiconductor device that can improve yield and reliability.
第１図は本発明の一実施例における半導体装置の上面図
、第２図は従来の半導体装置の上面図、第３図はＣＯＧ
工法によ辱接着部分の断面図である。
１・・・・・・切削領域、２・・・・・・能動領域、３
．４・・・・・・パッド、１０・・・・・・ガラス基板
、１１・・・・・・電極、１２・・・・・・半導体装置
基板、１３・・・・・・配線金属層、１４・・・・・・
絶縁保護膜、１５・・・・・・突起電極、１６・・・・
・・導電性接着剤、２０・・・・・・ダミーパッド。FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a top view of a conventional semiconductor device, and FIG. 3 is a COG
It is a cross-sectional view of the bonded part using the construction method. 1... Cutting area, 2... Active area, 3
．． 4... Pad, 10... Glass substrate, 11... Electrode, 12... Semiconductor device substrate, 13... Wiring metal layer, 14...
Insulating protective film, 15... protruding electrode, 16...
...Conductive adhesive, 20...Dummy pad.
Claims (1)
央付近を開口させて形成された絶縁保護膜を有する端子
電極のうち、外部回路との接続に供されるものと、接続
には供されないものとを有することを特徴とする半導体
装置。Among the electrodes formed of a part of the wiring metal layer and the terminal electrodes having an insulating protective film formed with an opening near the center of the electrode, those used for connection to an external circuit, and those used for connection 1. A semiconductor device characterized in that it has:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP746190A JPH03211838A (en) | 1990-01-17 | 1990-01-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP746190A JPH03211838A (en) | 1990-01-17 | 1990-01-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03211838A true JPH03211838A (en) | 1991-09-17 |
Family
ID=11666458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP746190A Pending JPH03211838A (en) | 1990-01-17 | 1990-01-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03211838A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025008730A (en) * | 2023-07-06 | 2025-01-20 | 日本特殊陶業株式会社 | Wiring Board |
-
1990
- 1990-01-17 JP JP746190A patent/JPH03211838A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025008730A (en) * | 2023-07-06 | 2025-01-20 | 日本特殊陶業株式会社 | Wiring Board |
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